1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/cpa2.h> 30 #include <lib/extensions/debug_v8p9.h> 31 #include <lib/extensions/fgt2.h> 32 #include <lib/extensions/idte3.h> 33 #include <lib/extensions/mpam.h> 34 #include <lib/extensions/pauth.h> 35 #include <lib/extensions/pmuv3.h> 36 #include <lib/extensions/sme.h> 37 #include <lib/extensions/spe.h> 38 #include <lib/extensions/sve.h> 39 #include <lib/extensions/sysreg128.h> 40 #include <lib/extensions/sys_reg_trace.h> 41 #include <lib/extensions/tcr2.h> 42 #include <lib/extensions/trbe.h> 43 #include <lib/extensions/trf.h> 44 #include <lib/utils.h> 45 46 #if ENABLE_FEAT_TWED 47 /* Make sure delay value fits within the range(0-15) */ 48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 49 #endif /* ENABLE_FEAT_TWED */ 50 51 per_world_context_t per_world_context[CPU_CONTEXT_NUM]; 52 PER_CPU_DEFINE(world_amu_regs_t, world_amu_ctx[CPU_CONTEXT_NUM]); 53 54 static void manage_extensions_nonsecure(cpu_context_t *ctx); 55 static void manage_extensions_secure(cpu_context_t *ctx); 56 57 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 58 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 59 { 60 u_register_t sctlr_elx, actlr_elx; 61 62 /* 63 * Initialise SCTLR_EL1 to the reset value corresponding to the target 64 * execution state setting all fields rather than relying on the hw. 65 * Some fields have architecturally UNKNOWN reset values and these are 66 * set to zero. 67 * 68 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 69 * 70 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 71 * required by PSCI specification) 72 */ 73 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 74 if (GET_RW(ep->spsr) == MODE_RW_64) { 75 sctlr_elx |= SCTLR_EL1_RES1; 76 } else { 77 /* 78 * If the target execution state is AArch32 then the following 79 * fields need to be set. 80 * 81 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 82 * instructions are not trapped to EL1. 83 * 84 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 85 * instructions are not trapped to EL1. 86 * 87 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 88 * CP15DMB, CP15DSB, and CP15ISB instructions. 89 */ 90 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 91 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 92 } 93 94 /* 95 * If workaround of errata 764081 for Cortex-A75 is used then set 96 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 97 */ 98 if (errata_a75_764081_applies()) { 99 sctlr_elx |= SCTLR_IESB_BIT; 100 } 101 102 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 103 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 104 105 /* 106 * Base the context ACTLR_EL1 on the current value, as it is 107 * implementation defined. The context restore process will write 108 * the value from the context to the actual register and can cause 109 * problems for processor cores that don't expect certain bits to 110 * be zero. 111 */ 112 actlr_elx = read_actlr_el1(); 113 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 114 } 115 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 116 117 /****************************************************************************** 118 * This function performs initializations that are specific to SECURE state 119 * and updates the cpu context specified by 'ctx'. 120 *****************************************************************************/ 121 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 122 { 123 u_register_t scr_el3; 124 el3_state_t *state; 125 126 state = get_el3state_ctx(ctx); 127 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 128 129 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 130 /* 131 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 132 * indicated by the interrupt routing model for BL31. 133 */ 134 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 135 #endif 136 137 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 138 if (is_feat_mte2_supported()) { 139 scr_el3 |= SCR_ATA_BIT; 140 } 141 142 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 143 144 /* 145 * Initialize EL1 context registers unless SPMC is running 146 * at S-EL2. 147 */ 148 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 149 setup_el1_context(ctx, ep); 150 #endif 151 152 manage_extensions_secure(ctx); 153 } 154 155 #if ENABLE_RME && IMAGE_BL31 156 /****************************************************************************** 157 * This function performs initializations that are specific to REALM state 158 * and updates the cpu context specified by 'ctx'. 159 * 160 * NOTE: any changes to this function must be verified by an RMMD maintainer. 161 *****************************************************************************/ 162 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 163 { 164 u_register_t scr_el3; 165 el3_state_t *state; 166 el2_sysregs_t *el2_ctx; 167 168 state = get_el3state_ctx(ctx); 169 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 170 el2_ctx = get_el2_sysregs_ctx(ctx); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM); 175 176 /* CSV2 version 2 and above */ 177 if (is_feat_csv2_2_supported()) { 178 /* Enable access to the SCXTNUM_ELx registers. */ 179 scr_el3 |= SCR_EnSCXT_BIT; 180 } 181 182 if (is_feat_sctlr2_supported()) { 183 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 184 * SCTLR2_ELx registers. 185 */ 186 scr_el3 |= SCR_SCTLR2En_BIT; 187 } 188 189 if (is_feat_d128_supported()) { 190 /* 191 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 192 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 193 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 194 */ 195 scr_el3 |= SCR_D128En_BIT; 196 } 197 198 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 199 200 if (is_feat_fgt2_supported()) { 201 fgt2_enable(ctx); 202 } 203 204 if (is_feat_debugv8p9_supported()) { 205 debugv8p9_extended_bp_wp_enable(ctx); 206 } 207 208 if (is_feat_brbe_supported()) { 209 brbe_enable(ctx); 210 } 211 212 /* 213 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world. 214 */ 215 if (is_feat_sme_supported()) { 216 sme_enable(ctx); 217 } 218 219 if (is_feat_spe_supported()) { 220 spe_disable_realm(ctx); 221 } 222 223 if (is_feat_trbe_supported()) { 224 trbe_disable_realm(ctx); 225 } 226 } 227 #endif /* ENABLE_RME && IMAGE_BL31 */ 228 229 /****************************************************************************** 230 * This function performs initializations that are specific to NON-SECURE state 231 * and updates the cpu context specified by 'ctx'. 232 *****************************************************************************/ 233 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 234 { 235 u_register_t scr_el3; 236 el3_state_t *state; 237 238 state = get_el3state_ctx(ctx); 239 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 240 241 /* SCR_NS: Set the NS bit */ 242 scr_el3 |= SCR_NS_BIT; 243 244 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 245 if (is_feat_mte2_supported()) { 246 scr_el3 |= SCR_ATA_BIT; 247 } 248 249 /* 250 * Pointer Authentication feature, if present, is always enabled by 251 * default for Non secure lower exception levels. We do not have an 252 * explicit flag to set it. To prevent the leakage between the worlds 253 * during world switch, we enable it only for the non-secure world. 254 * 255 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 256 * exception levels of secure and realm worlds. 257 * 258 * If the Secure/realm world wants to use pointer authentication, 259 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 260 * it will be enabled globally for all the contexts. 261 * 262 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 263 * other than EL3 264 * 265 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 266 * than EL3 267 */ 268 if (!is_ctx_pauth_supported()) { 269 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 270 } 271 272 #if HANDLE_EA_EL3_FIRST_NS 273 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 274 scr_el3 |= SCR_EA_BIT; 275 #endif 276 277 #if RAS_TRAP_NS_ERR_REC_ACCESS 278 /* 279 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 280 * and RAS ERX registers from EL1 and EL2(from any security state) 281 * are trapped to EL3. 282 * Set here to trap only for NS EL1/EL2 283 */ 284 scr_el3 |= SCR_TERR_BIT; 285 #endif 286 287 /* CSV2 version 2 and above */ 288 if (is_feat_csv2_2_supported()) { 289 /* Enable access to the SCXTNUM_ELx registers. */ 290 scr_el3 |= SCR_EnSCXT_BIT; 291 } 292 293 #ifdef IMAGE_BL31 294 /* 295 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 296 * indicated by the interrupt routing model for BL31. 297 */ 298 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 299 #endif 300 301 if (is_feat_the_supported()) { 302 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 303 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 304 */ 305 scr_el3 |= SCR_RCWMASKEn_BIT; 306 } 307 308 if (is_feat_sctlr2_supported()) { 309 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 310 * SCTLR2_ELx registers. 311 */ 312 scr_el3 |= SCR_SCTLR2En_BIT; 313 } 314 315 if (is_feat_d128_supported()) { 316 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 317 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 318 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 319 */ 320 scr_el3 |= SCR_D128En_BIT; 321 } 322 323 if (is_feat_fpmr_supported()) { 324 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 325 * register. 326 */ 327 scr_el3 |= SCR_EnFPM_BIT; 328 } 329 330 if (is_feat_aie_supported()) { 331 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2 332 * system registers from NS world. 333 */ 334 scr_el3 |= SCR_AIEn_BIT; 335 } 336 337 if (is_feat_pfar_supported()) { 338 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR 339 * system registers from NS world. 340 */ 341 scr_el3 |= SCR_PFAREn_BIT; 342 } 343 344 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 345 346 /* Initialize EL2 context registers */ 347 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 348 if (is_feat_hcx_supported()) { 349 /* 350 * Initialize register HCRX_EL2 with its init value. 351 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 352 * chance that this can lead to unexpected behavior in lower 353 * ELs that have not been updated since the introduction of 354 * this feature if not properly initialized, especially when 355 * it comes to those bits that enable/disable traps. 356 */ 357 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 358 HCRX_EL2_INIT_VAL); 359 } 360 361 if (is_feat_fgt_supported()) { 362 /* 363 * Initialize HFG*_EL2 registers with a default value so legacy 364 * systems unaware of FEAT_FGT do not get trapped due to their lack 365 * of initialization for this feature. 366 */ 367 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 368 HFGITR_EL2_INIT_VAL); 369 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 370 HFGRTR_EL2_INIT_VAL); 371 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 372 HFGWTR_EL2_INIT_VAL); 373 } 374 #else 375 /* Initialize EL1 context registers */ 376 setup_el1_context(ctx, ep); 377 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 378 379 manage_extensions_nonsecure(ctx); 380 } 381 382 /******************************************************************************* 383 * The following function performs initialization of the cpu_context 'ctx' 384 * for first use that is common to all security states, and sets the 385 * initial entrypoint state as specified by the entry_point_info structure. 386 * 387 * The EE and ST attributes are used to configure the endianness and secure 388 * timer availability for the new execution context. 389 ******************************************************************************/ 390 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 391 { 392 u_register_t scr_el3; 393 u_register_t mdcr_el3; 394 el3_state_t *state; 395 gp_regs_t *gp_regs; 396 397 state = get_el3state_ctx(ctx); 398 399 /* Clear any residual register values from the context */ 400 zeromem(ctx, sizeof(*ctx)); 401 402 /* 403 * The lower-EL context is zeroed so that no stale values leak to a world. 404 * It is assumed that an all-zero lower-EL context is good enough for it 405 * to boot correctly. However, there are very few registers where this 406 * is not true and some values need to be recreated. 407 */ 408 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 409 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 410 411 /* 412 * These bits are set in the gicv3 driver. Losing them (especially the 413 * SRE bit) is problematic for all worlds. Henceforth recreate them. 414 */ 415 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 416 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 417 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 418 419 /* 420 * The actlr_el2 register can be initialized in platform's reset handler 421 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 422 */ 423 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 424 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 425 426 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 427 scr_el3 = SCR_RESET_VAL; 428 429 /* 430 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 431 * EL2, EL1 and EL0 are not trapped to EL3. 432 * 433 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 434 * EL2, EL1 and EL0 are not trapped to EL3. 435 * 436 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 437 * both Security states and both Execution states. 438 * 439 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 440 * Non-secure memory. 441 */ 442 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 443 444 scr_el3 |= SCR_SIF_BIT; 445 446 /* 447 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 448 * Exception level as specified by SPSR. 449 */ 450 if (GET_RW(ep->spsr) == MODE_RW_64) { 451 scr_el3 |= SCR_RW_BIT; 452 } 453 454 /* 455 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 456 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 457 * next mode is Hyp. 458 */ 459 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 460 || ((GET_RW(ep->spsr) != MODE_RW_64) 461 && (GET_M32(ep->spsr) == MODE32_hyp))) { 462 scr_el3 |= SCR_HCE_BIT; 463 } 464 465 /* 466 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 467 * Secure timer registers to EL3, from AArch64 state only, if specified 468 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 469 * bit always behaves as 1 (i.e. secure physical timer register access 470 * is not trapped) 471 */ 472 if (EP_GET_ST(ep->h.attr) != 0U) { 473 scr_el3 |= SCR_ST_BIT; 474 } 475 476 /* 477 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 478 * SCR_EL3.HXEn. 479 */ 480 if (is_feat_hcx_supported()) { 481 scr_el3 |= SCR_HXEn_BIT; 482 } 483 484 /* 485 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 486 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 487 * SCR_EL3.EnAS0. 488 */ 489 if (is_feat_ls64_accdata_supported()) { 490 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 491 } 492 493 /* 494 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 495 * registers are trapped to EL3. 496 */ 497 if (is_feat_rng_trap_supported()) { 498 scr_el3 |= SCR_TRNDR_BIT; 499 } 500 501 #if FAULT_INJECTION_SUPPORT 502 /* Enable fault injection from lower ELs */ 503 scr_el3 |= SCR_FIEN_BIT; 504 #endif 505 506 /* 507 * Enable Pointer Authentication globally for all the worlds. 508 * 509 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 510 * other than EL3 511 * 512 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 513 * than EL3 514 */ 515 if (is_ctx_pauth_supported()) { 516 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 517 } 518 519 /* 520 * SCR_EL3.PIEN: Enable permission indirection and overlay 521 * registers for AArch64 if present. 522 */ 523 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 524 scr_el3 |= SCR_PIEN_BIT; 525 } 526 527 /* SCR_EL3.GCSEn: Enable GCS registers. */ 528 if (is_feat_gcs_supported()) { 529 scr_el3 |= SCR_GCSEn_BIT; 530 } 531 532 /* SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps */ 533 if (is_feat_fgt_supported()) { 534 scr_el3 |= SCR_FGTEN_BIT; 535 } 536 537 /* SCR_EL3.ECVEn: Do not trap the CNTPOFF_EL2 register */ 538 if (is_feat_ecv_supported()) { 539 scr_el3 |= SCR_ECVEN_BIT; 540 } 541 542 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 543 if (is_feat_twed_supported()) { 544 /* Set delay in SCR_EL3 */ 545 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 546 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 547 << SCR_TWEDEL_SHIFT); 548 549 /* Enable WFE delay */ 550 scr_el3 |= SCR_TWEDEn_BIT; 551 } 552 553 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 554 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 555 if (is_feat_sel2_supported()) { 556 scr_el3 |= SCR_EEL2_BIT; 557 } 558 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 559 560 if (is_feat_mec_supported()) { 561 scr_el3 |= SCR_MECEn_BIT; 562 } 563 564 /* 565 * Populate EL3 state so that we've the right context 566 * before doing ERET 567 */ 568 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 569 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 570 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 571 572 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 573 mdcr_el3 = MDCR_EL3_RESET_VAL; 574 575 /* --------------------------------------------------------------------- 576 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 577 * Some fields are architecturally UNKNOWN on reset. 578 * 579 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 580 * Debug exceptions, other than Breakpoint Instruction exceptions, are 581 * disabled from all ELs in Secure state. 582 * 583 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 584 * privileged debug from S-EL1. 585 * 586 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 587 * access to the powerdown debug registers do not trap to EL3. 588 * 589 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 590 * debug registers, other than those registers that are controlled by 591 * MDCR_EL3.TDOSA. 592 */ 593 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 594 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 595 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 596 597 #if IMAGE_BL31 598 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 599 if (is_feat_trf_supported()) { 600 trf_enable(ctx); 601 } 602 603 if (is_feat_tcr2_supported()) { 604 tcr2_enable(ctx); 605 } 606 607 pmuv3_enable(ctx); 608 609 if (is_feat_idte3_supported()) { 610 idte3_enable(ctx); 611 } 612 613 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31 614 /* 615 * Initialize SCTLR_EL2 context register with reset value. 616 */ 617 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 618 #endif /* CTX_INCLUDE_EL2_REGS */ 619 #endif /* IMAGE_BL31 */ 620 621 /* 622 * Store the X0-X7 value from the entrypoint into the context 623 * Use memcpy as we are in control of the layout of the structures 624 */ 625 gp_regs = get_gpregs_ctx(ctx); 626 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 627 } 628 629 /******************************************************************************* 630 * Context management library initialization routine. This library is used by 631 * runtime services to share pointers to 'cpu_context' structures for secure 632 * non-secure and realm states. Management of the structures and their associated 633 * memory is not done by the context management library e.g. the PSCI service 634 * manages the cpu context used for entry from and exit to the non-secure state. 635 * The Secure payload dispatcher service manages the context(s) corresponding to 636 * the secure state. It also uses this library to get access to the non-secure 637 * state cpu context pointers. 638 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 639 * which will be used for programming an entry into a lower EL. The same context 640 * will be used to save state upon exception entry from that EL. 641 ******************************************************************************/ 642 void __init cm_init(void) 643 { 644 /* 645 * The context management library has only global data to initialize, but 646 * that will be done when the BSS is zeroed out. 647 */ 648 } 649 650 /******************************************************************************* 651 * This is the high-level function used to initialize the cpu_context 'ctx' for 652 * first use. It performs initializations that are common to all security states 653 * and initializations specific to the security state specified in 'ep' 654 ******************************************************************************/ 655 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 656 { 657 size_t security_state; 658 659 assert(ctx != NULL); 660 661 /* 662 * Perform initializations that are common 663 * to all security states 664 */ 665 setup_context_common(ctx, ep); 666 667 security_state = GET_SECURITY_STATE(ep->h.attr); 668 669 /* Perform security state specific initializations */ 670 switch (security_state) { 671 case SECURE: 672 setup_secure_context(ctx, ep); 673 break; 674 #if ENABLE_RME && IMAGE_BL31 675 case REALM: 676 setup_realm_context(ctx, ep); 677 break; 678 #endif 679 case NON_SECURE: 680 setup_ns_context(ctx, ep); 681 break; 682 default: 683 ERROR("Invalid security state\n"); 684 panic(); 685 break; 686 } 687 } 688 689 /******************************************************************************* 690 * Enable architecture extensions for EL3 execution. This function only updates 691 * registers in-place which are expected to either never change or be 692 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 693 ******************************************************************************/ 694 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx) 695 { 696 if (is_feat_pauth_supported()) { 697 pauth_init_enable_el3(); 698 } 699 700 #if IMAGE_BL31 701 if (is_feat_sve_supported()) { 702 sve_init_el3(); 703 } 704 705 if (is_feat_amu_supported()) { 706 amu_init_el3(my_idx); 707 } 708 709 if (is_feat_sme_supported()) { 710 sme_init_el3(); 711 } 712 713 if (is_feat_mpam_supported()) { 714 mpam_init_el3(); 715 } 716 717 if (is_feat_cpa2_supported()) { 718 cpa2_enable_el3(); 719 } 720 721 pmuv3_init_el3(); 722 723 /* NOTE: must be done last, makes the configuration immutable */ 724 if (is_feat_fgwte3_supported()) { 725 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL); 726 } 727 #endif /* IMAGE_BL31 */ 728 } 729 730 /****************************************************************************** 731 * Function to initialise the registers with the RESET values in the context 732 * memory, which are maintained per world. 733 ******************************************************************************/ 734 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 735 { 736 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL; 737 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 738 } 739 740 /******************************************************************************* 741 * Initialise per_world_context for Non-Secure world. 742 * This function enables the architecture extensions, which have same value 743 * across the cores for the non-secure world. 744 ******************************************************************************/ 745 static void manage_extensions_nonsecure_per_world(void) 746 { 747 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 748 749 #if IMAGE_BL31 750 if (is_feat_sme_supported()) { 751 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 752 } 753 754 if (is_feat_sve_supported()) { 755 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 756 } 757 758 if (is_feat_amu_supported()) { 759 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 760 } 761 762 if (is_feat_sys_reg_trace_supported()) { 763 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 764 } 765 766 if (is_feat_mpam_supported()) { 767 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 768 } 769 770 if (is_feat_idte3_supported()) { 771 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS); 772 } 773 #endif /* IMAGE_BL31 */ 774 } 775 776 /******************************************************************************* 777 * Initialise per_world_context for Secure world. 778 * This function enables the architecture extensions, which have same value 779 * across the cores for the secure world. 780 ******************************************************************************/ 781 static void manage_extensions_secure_per_world(void) 782 { 783 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 784 785 #if IMAGE_BL31 786 if (is_feat_sme_supported()) { 787 788 if (ENABLE_SME_FOR_SWD) { 789 /* 790 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 791 * SME, SVE, and FPU/SIMD context properly managed. 792 */ 793 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 794 } else { 795 /* 796 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 797 * world can safely use the associated registers. 798 */ 799 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 800 } 801 } 802 if (is_feat_sve_supported()) { 803 if (ENABLE_SVE_FOR_SWD) { 804 /* 805 * Enable SVE and FPU in secure context, SPM must ensure 806 * that the SVE and FPU register contexts are properly managed. 807 */ 808 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 809 } else { 810 /* 811 * Disable SVE and FPU in secure context so non-secure world 812 * can safely use them. 813 */ 814 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 815 } 816 } 817 818 /* NS can access this but Secure shouldn't */ 819 if (is_feat_sys_reg_trace_supported()) { 820 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 821 } 822 823 if (is_feat_idte3_supported()) { 824 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE); 825 } 826 #endif /* IMAGE_BL31 */ 827 } 828 829 static void manage_extensions_realm_per_world(void) 830 { 831 #if ENABLE_RME && IMAGE_BL31 832 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 833 834 if (is_feat_sve_supported()) { 835 /* 836 * Enable SVE and FPU in realm context when it is enabled for NS. 837 * Realm manager must ensure that the SVE and FPU register 838 * contexts are properly managed. 839 */ 840 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 841 } 842 843 /* NS can access this but Realm shouldn't */ 844 if (is_feat_sys_reg_trace_supported()) { 845 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 846 } 847 848 /* 849 * If SME/SME2 is supported and enabled for NS world, then disable trapping 850 * of SME instructions for Realm world. RMM will save/restore required 851 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 852 */ 853 if (is_feat_sme_supported()) { 854 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 855 } 856 857 /* 858 * If FEAT_MPAM is supported and enabled, then disable trapping access 859 * to the MPAM registers for Realm world. Instead, RMM will configure 860 * the access to be trapped by itself so it can inject undefined aborts 861 * back to the Realm. 862 */ 863 if (is_feat_mpam_supported()) { 864 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 865 } 866 867 if (is_feat_idte3_supported()) { 868 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM); 869 } 870 #endif /* ENABLE_RME && IMAGE_BL31 */ 871 } 872 873 void cm_manage_extensions_per_world(void) 874 { 875 manage_extensions_nonsecure_per_world(); 876 manage_extensions_secure_per_world(); 877 manage_extensions_realm_per_world(); 878 } 879 880 void cm_init_percpu_once_regs(void) 881 { 882 #if IMAGE_BL31 883 if (is_feat_idte3_supported()) { 884 idte3_init_percpu_once_regs(CPU_CONTEXT_NS); 885 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE); 886 #if ENABLE_RME 887 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM); 888 #endif /* ENABLE_RME */ 889 } 890 #endif /* IMAGE_BL31 */ 891 } 892 893 /******************************************************************************* 894 * Enable architecture extensions on first entry to Non-secure world. 895 ******************************************************************************/ 896 static void manage_extensions_nonsecure(cpu_context_t *ctx) 897 { 898 #if IMAGE_BL31 899 /* NOTE: registers are not context switched */ 900 if (is_feat_amu_supported()) { 901 amu_enable(ctx); 902 } 903 904 if (is_feat_sme_supported()) { 905 sme_enable(ctx); 906 } 907 908 if (is_feat_fgt2_supported()) { 909 fgt2_enable(ctx); 910 } 911 912 if (is_feat_debugv8p9_supported()) { 913 debugv8p9_extended_bp_wp_enable(ctx); 914 } 915 916 if (is_feat_spe_supported()) { 917 spe_enable_ns(ctx); 918 } 919 920 if (is_feat_trbe_supported()) { 921 if (check_if_trbe_disable_affected_core()) { 922 trbe_disable_ns(ctx); 923 } else { 924 trbe_enable_ns(ctx); 925 } 926 } 927 928 if (is_feat_brbe_supported()) { 929 brbe_enable(ctx); 930 } 931 #endif /* IMAGE_BL31 */ 932 } 933 934 #if INIT_UNUSED_NS_EL2 935 /******************************************************************************* 936 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 937 * world when EL2 is empty and unused. 938 ******************************************************************************/ 939 static void manage_extensions_nonsecure_el2_unused(void) 940 { 941 #if IMAGE_BL31 942 if (is_feat_spe_supported()) { 943 spe_init_el2_unused(); 944 } 945 946 if (is_feat_amu_supported()) { 947 amu_init_el2_unused(); 948 } 949 950 if (is_feat_mpam_supported()) { 951 mpam_init_el2_unused(); 952 } 953 954 if (is_feat_trbe_supported()) { 955 trbe_init_el2_unused(); 956 } 957 958 if (is_feat_sys_reg_trace_supported()) { 959 sys_reg_trace_init_el2_unused(); 960 } 961 962 if (is_feat_trf_supported()) { 963 trf_init_el2_unused(); 964 } 965 966 pmuv3_init_el2_unused(); 967 968 if (is_feat_sve_supported()) { 969 sve_init_el2_unused(); 970 } 971 972 if (is_feat_sme_supported()) { 973 sme_init_el2_unused(); 974 } 975 976 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 977 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 978 } 979 980 if (is_feat_pauth_supported()) { 981 pauth_enable_el2(); 982 } 983 #endif /* IMAGE_BL31 */ 984 } 985 #endif /* INIT_UNUSED_NS_EL2 */ 986 987 /******************************************************************************* 988 * Enable architecture extensions on first entry to Secure world. 989 ******************************************************************************/ 990 static void manage_extensions_secure(cpu_context_t *ctx) 991 { 992 #if IMAGE_BL31 993 if (is_feat_sme_supported()) { 994 if (ENABLE_SME_FOR_SWD) { 995 /* 996 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 997 * must ensure SME, SVE, and FPU/SIMD context properly managed. 998 */ 999 sme_init_el3(); 1000 sme_enable(ctx); 1001 } else { 1002 /* 1003 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 1004 * world can safely use the associated registers. 1005 */ 1006 sme_disable(ctx); 1007 } 1008 } 1009 1010 if (is_feat_spe_supported()) { 1011 spe_disable_secure(ctx); 1012 } 1013 1014 if (is_feat_trbe_supported()) { 1015 trbe_disable_secure(ctx); 1016 } 1017 #endif /* IMAGE_BL31 */ 1018 } 1019 1020 /******************************************************************************* 1021 * The following function initializes the cpu_context for the current CPU 1022 * for first use, and sets the initial entrypoint state as specified by the 1023 * entry_point_info structure. 1024 ******************************************************************************/ 1025 void cm_init_my_context(const entry_point_info_t *ep) 1026 { 1027 cpu_context_t *ctx; 1028 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 1029 cm_setup_context(ctx, ep); 1030 } 1031 1032 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 1033 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 1034 { 1035 #if INIT_UNUSED_NS_EL2 1036 u_register_t hcr_el2 = HCR_RESET_VAL; 1037 u_register_t mdcr_el2; 1038 u_register_t scr_el3; 1039 1040 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1041 1042 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 1043 if ((scr_el3 & SCR_RW_BIT) != 0U) { 1044 hcr_el2 |= HCR_RW_BIT; 1045 } 1046 1047 write_hcr_el2(hcr_el2); 1048 1049 /* 1050 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1051 * All fields have architecturally UNKNOWN reset values. 1052 */ 1053 write_cptr_el2(CPTR_EL2_RESET_VAL); 1054 1055 /* 1056 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1057 * reset and are set to zero except for field(s) listed below. 1058 * 1059 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1060 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1061 * 1062 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1063 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1064 */ 1065 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1066 1067 /* 1068 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1069 * UNKNOWN value. 1070 */ 1071 write_cntvoff_el2(0); 1072 1073 /* 1074 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1075 * respectively. 1076 */ 1077 write_vpidr_el2(read_midr_el1()); 1078 write_vmpidr_el2(read_mpidr_el1()); 1079 1080 /* 1081 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1082 * 1083 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1084 * translation is disabled, cache maintenance operations depend on the 1085 * VMID. 1086 * 1087 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1088 * disabled. 1089 */ 1090 write_vttbr_el2(VTTBR_RESET_VAL & 1091 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1092 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1093 1094 /* 1095 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1096 * Some fields are architecturally UNKNOWN on reset. 1097 * 1098 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1099 * register accesses to the Debug ROM registers are not trapped to EL2. 1100 * 1101 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1102 * accesses to the powerdown debug registers are not trapped to EL2. 1103 * 1104 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1105 * debug registers do not trap to EL2. 1106 * 1107 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1108 * EL2. 1109 */ 1110 mdcr_el2 = MDCR_EL2_RESET_VAL & 1111 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1112 MDCR_EL2_TDE_BIT); 1113 1114 write_mdcr_el2(mdcr_el2); 1115 1116 /* 1117 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1118 * 1119 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1120 * EL1 accesses to System registers do not trap to EL2. 1121 */ 1122 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1123 1124 /* 1125 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1126 * reset. 1127 * 1128 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1129 * and prevent timer interrupts. 1130 */ 1131 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1132 1133 manage_extensions_nonsecure_el2_unused(); 1134 #endif /* INIT_UNUSED_NS_EL2 */ 1135 } 1136 1137 /******************************************************************************* 1138 * Prepare the CPU system registers for first entry into realm, secure, or 1139 * normal world. 1140 * 1141 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1142 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1143 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1144 * For all entries, the EL1 registers are initialized from the cpu_context 1145 ******************************************************************************/ 1146 void cm_prepare_el3_exit(size_t security_state) 1147 { 1148 u_register_t sctlr_el2, scr_el3; 1149 cpu_context_t *ctx = cm_get_context(security_state); 1150 1151 assert(ctx != NULL); 1152 1153 if (security_state == NON_SECURE) { 1154 uint64_t el2_implemented = el_implemented(2); 1155 1156 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1157 CTX_SCR_EL3); 1158 1159 if (el2_implemented != EL_IMPL_NONE) { 1160 1161 /* 1162 * If context is not being used for EL2, initialize 1163 * HCRX_EL2 with its init value here. 1164 */ 1165 if (is_feat_hcx_supported()) { 1166 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1167 } 1168 1169 /* 1170 * Initialize Fine-grained trap registers introduced 1171 * by FEAT_FGT so all traps are initially disabled when 1172 * switching to EL2 or a lower EL, preventing undesired 1173 * behavior. 1174 */ 1175 if (is_feat_fgt_supported()) { 1176 /* 1177 * Initialize HFG*_EL2 registers with a default 1178 * value so legacy systems unaware of FEAT_FGT 1179 * do not get trapped due to their lack of 1180 * initialization for this feature. 1181 */ 1182 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1183 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1184 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1185 } 1186 1187 /* Condition to ensure EL2 is being used. */ 1188 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1189 /* Initialize SCTLR_EL2 register with reset value. */ 1190 sctlr_el2 = SCTLR_EL2_RES1; 1191 1192 /* 1193 * If workaround of errata 764081 for Cortex-A75 1194 * is used then set SCTLR_EL2.IESB to enable 1195 * Implicit Error Synchronization Barrier. 1196 */ 1197 if (errata_a75_764081_applies()) { 1198 sctlr_el2 |= SCTLR_IESB_BIT; 1199 } 1200 1201 write_sctlr_el2(sctlr_el2); 1202 } else { 1203 /* 1204 * (scr_el3 & SCR_HCE_BIT==0) 1205 * EL2 implemented but unused. 1206 */ 1207 init_nonsecure_el2_unused(ctx); 1208 } 1209 } 1210 1211 if (is_feat_fgwte3_supported()) { 1212 /* 1213 * TCR_EL3 and ACTLR_EL3 could be overwritten 1214 * by platforms and hence is locked a bit late. 1215 */ 1216 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL); 1217 } 1218 } 1219 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1 1220 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1221 cm_el1_sysregs_context_restore(security_state); 1222 #endif 1223 cm_set_next_eret_context(security_state); 1224 } 1225 1226 /* Assumes prepare_el3_entry() has disabled counters 2 and 3 */ 1227 void cm_sysregs_context_save_amu(unsigned int security_state) 1228 { 1229 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1230 1231 ctx->amevcntr02_el0 = read_amevcntr02_el0(); 1232 ctx->amevcntr03_el0 = read_amevcntr03_el0(); 1233 } 1234 1235 void cm_sysregs_context_restore_amu(unsigned int security_state) 1236 { 1237 world_amu_regs_t *ctx = PER_CPU_CUR(world_amu_ctx[get_cpu_context_index(security_state)]); 1238 1239 write_amevcntr02_el0(ctx->amevcntr02_el0); 1240 write_amevcntr03_el0(ctx->amevcntr03_el0); 1241 } 1242 1243 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1244 1245 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1246 { 1247 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1248 if (is_feat_amu_supported()) { 1249 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1250 } 1251 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1252 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1253 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1254 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1255 } 1256 1257 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1258 { 1259 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1260 if (is_feat_amu_supported()) { 1261 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1262 } 1263 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1264 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1265 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1266 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1267 } 1268 1269 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1270 { 1271 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1272 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1273 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1274 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1275 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1276 } 1277 1278 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1279 { 1280 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1281 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1282 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1283 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1284 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1285 } 1286 1287 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1288 { 1289 u_register_t mpam_idr = read_mpamidr_el1(); 1290 1291 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1292 1293 /* 1294 * The context registers that we intend to save would be part of the 1295 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1296 */ 1297 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1298 return; 1299 } 1300 1301 /* 1302 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1303 * MPAMIDR_HAS_HCR_BIT == 1. 1304 */ 1305 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1306 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1307 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1308 1309 /* 1310 * The number of MPAMVPM registers is implementation defined, their 1311 * number is stored in the MPAMIDR_EL1 register. 1312 */ 1313 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1314 case 7: 1315 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1316 __fallthrough; 1317 case 6: 1318 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1319 __fallthrough; 1320 case 5: 1321 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1322 __fallthrough; 1323 case 4: 1324 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1325 __fallthrough; 1326 case 3: 1327 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1328 __fallthrough; 1329 case 2: 1330 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1331 __fallthrough; 1332 case 1: 1333 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1334 break; 1335 } 1336 } 1337 1338 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1339 { 1340 u_register_t mpam_idr = read_mpamidr_el1(); 1341 1342 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1343 1344 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1345 return; 1346 } 1347 1348 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1349 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1350 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1351 1352 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1353 case 7: 1354 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1355 __fallthrough; 1356 case 6: 1357 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1358 __fallthrough; 1359 case 5: 1360 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1361 __fallthrough; 1362 case 4: 1363 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1364 __fallthrough; 1365 case 3: 1366 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1367 __fallthrough; 1368 case 2: 1369 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1370 __fallthrough; 1371 case 1: 1372 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1373 break; 1374 } 1375 } 1376 1377 /* --------------------------------------------------------------------------- 1378 * The following registers are not added: 1379 * ICH_AP0R<n>_EL2 1380 * ICH_AP1R<n>_EL2 1381 * ICH_LR<n>_EL2 1382 * 1383 * NOTE: For a system with S-EL2 present but not enabled, accessing 1384 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1385 * SCR_EL3.NS = 1 before accessing this register. 1386 * --------------------------------------------------------------------------- 1387 */ 1388 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1389 { 1390 u_register_t scr_el3 = read_scr_el3(); 1391 1392 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1393 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1394 #else 1395 write_scr_el3(scr_el3 | SCR_NS_BIT); 1396 isb(); 1397 1398 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1399 1400 write_scr_el3(scr_el3); 1401 isb(); 1402 #endif 1403 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1404 1405 if (errata_ich_vmcr_el2_applies()) { 1406 if (security_state == SECURE) { 1407 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1408 } else { 1409 write_scr_el3(scr_el3 | SCR_NS_BIT); 1410 } 1411 isb(); 1412 } 1413 1414 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1415 1416 if (errata_ich_vmcr_el2_applies()) { 1417 write_scr_el3(scr_el3); 1418 isb(); 1419 } 1420 } 1421 1422 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1423 { 1424 u_register_t scr_el3 = read_scr_el3(); 1425 1426 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1427 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1428 #else 1429 write_scr_el3(scr_el3 | SCR_NS_BIT); 1430 isb(); 1431 1432 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1433 1434 write_scr_el3(scr_el3); 1435 isb(); 1436 #endif 1437 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1438 1439 if (errata_ich_vmcr_el2_applies()) { 1440 if (security_state == SECURE) { 1441 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1442 } else { 1443 write_scr_el3(scr_el3 | SCR_NS_BIT); 1444 } 1445 isb(); 1446 } 1447 1448 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1449 1450 if (errata_ich_vmcr_el2_applies()) { 1451 write_scr_el3(scr_el3); 1452 isb(); 1453 } 1454 } 1455 1456 /* ----------------------------------------------------- 1457 * The following registers are not added: 1458 * AMEVCNTVOFF0<n>_EL2 1459 * AMEVCNTVOFF1<n>_EL2 1460 * ----------------------------------------------------- 1461 */ 1462 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1463 { 1464 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1465 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1466 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1467 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1468 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1469 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1470 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1471 if (CTX_INCLUDE_AARCH32_REGS) { 1472 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1473 } 1474 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1475 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1476 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1477 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1478 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1479 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1480 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1481 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1482 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1483 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1484 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1485 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1486 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1487 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1488 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1489 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1490 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1491 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1492 1493 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1494 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1495 } 1496 1497 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1498 { 1499 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1500 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1501 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1502 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1503 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1504 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1505 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1506 if (CTX_INCLUDE_AARCH32_REGS) { 1507 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1508 } 1509 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1510 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1511 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1512 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1513 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1514 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1515 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1516 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1517 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1518 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1519 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1520 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1521 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1522 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1523 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1524 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1525 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1526 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1527 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1528 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1529 } 1530 1531 /******************************************************************************* 1532 * Save EL2 sysreg context 1533 ******************************************************************************/ 1534 void cm_el2_sysregs_context_save(uint32_t security_state) 1535 { 1536 cpu_context_t *ctx; 1537 el2_sysregs_t *el2_sysregs_ctx; 1538 1539 ctx = cm_get_context(security_state); 1540 assert(ctx != NULL); 1541 1542 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1543 1544 el2_sysregs_context_save_common(el2_sysregs_ctx); 1545 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1546 1547 if (is_feat_mte2_supported()) { 1548 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1549 } 1550 1551 if (is_feat_mpam_supported()) { 1552 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1553 } 1554 1555 if (is_feat_fgt_supported()) { 1556 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1557 } 1558 1559 if (is_feat_fgt2_supported()) { 1560 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1561 } 1562 1563 if (is_feat_ecv_v2_supported()) { 1564 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1565 } 1566 1567 if (is_feat_vhe_supported()) { 1568 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1569 read_contextidr_el2()); 1570 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1571 } 1572 1573 if (is_feat_ras_supported()) { 1574 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1575 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1576 } 1577 1578 if (is_feat_nv2_supported()) { 1579 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1580 } 1581 1582 if (is_feat_trf_supported()) { 1583 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1584 } 1585 1586 if (is_feat_csv2_2_supported()) { 1587 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1588 read_scxtnum_el2()); 1589 } 1590 1591 if (is_feat_hcx_supported()) { 1592 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1593 } 1594 1595 if (is_feat_tcr2_supported()) { 1596 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1597 } 1598 1599 if (is_feat_s1pie_supported()) { 1600 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1601 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1602 } 1603 1604 if (is_feat_s1poe_supported()) { 1605 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1606 } 1607 1608 if (is_feat_brbe_supported()) { 1609 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1610 } 1611 1612 if (is_feat_s2pie_supported()) { 1613 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1614 } 1615 1616 if (is_feat_gcs_supported()) { 1617 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1618 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1619 } 1620 1621 if (is_feat_sctlr2_supported()) { 1622 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1623 } 1624 1625 if (is_feat_amu_supported()) { 1626 cm_sysregs_context_save_amu(security_state); 1627 } 1628 } 1629 1630 /******************************************************************************* 1631 * Restore EL2 sysreg context 1632 ******************************************************************************/ 1633 void cm_el2_sysregs_context_restore(uint32_t security_state) 1634 { 1635 cpu_context_t *ctx; 1636 el2_sysregs_t *el2_sysregs_ctx; 1637 1638 ctx = cm_get_context(security_state); 1639 assert(ctx != NULL); 1640 1641 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1642 1643 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1644 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1645 1646 if (is_feat_mte2_supported()) { 1647 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1648 } 1649 1650 if (is_feat_mpam_supported()) { 1651 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1652 } 1653 1654 if (is_feat_fgt_supported()) { 1655 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1656 } 1657 1658 if (is_feat_fgt2_supported()) { 1659 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1660 } 1661 1662 if (is_feat_ecv_v2_supported()) { 1663 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1664 } 1665 1666 if (is_feat_vhe_supported()) { 1667 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1668 contextidr_el2)); 1669 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1670 } 1671 1672 if (is_feat_ras_supported()) { 1673 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1674 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1675 } 1676 1677 if (is_feat_nv2_supported()) { 1678 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1679 } 1680 1681 if (is_feat_trf_supported()) { 1682 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1683 } 1684 1685 if (is_feat_csv2_2_supported()) { 1686 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1687 scxtnum_el2)); 1688 } 1689 1690 if (is_feat_hcx_supported()) { 1691 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1692 } 1693 1694 if (is_feat_tcr2_supported()) { 1695 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1696 } 1697 1698 if (is_feat_s1pie_supported()) { 1699 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1700 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1701 } 1702 1703 if (is_feat_s1poe_supported()) { 1704 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1705 } 1706 1707 if (is_feat_s2pie_supported()) { 1708 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1709 } 1710 1711 if (is_feat_gcs_supported()) { 1712 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1713 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1714 } 1715 1716 if (is_feat_sctlr2_supported()) { 1717 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1718 } 1719 1720 if (is_feat_brbe_supported()) { 1721 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1722 } 1723 1724 if (is_feat_amu_supported()) { 1725 cm_sysregs_context_restore_amu(security_state); 1726 } 1727 } 1728 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1729 1730 /******************************************************************************* 1731 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1732 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1733 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1734 * cm_prepare_el3_exit function. 1735 ******************************************************************************/ 1736 void cm_prepare_el3_exit_ns(void) 1737 { 1738 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1739 #if ENABLE_ASSERTIONS 1740 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1741 assert(ctx != NULL); 1742 1743 /* Assert that EL2 is used. */ 1744 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1745 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1746 (el_implemented(2U) != EL_IMPL_NONE)); 1747 #endif /* ENABLE_ASSERTIONS */ 1748 1749 /* Restore EL2 sysreg contexts */ 1750 cm_el2_sysregs_context_restore(NON_SECURE); 1751 cm_set_next_eret_context(NON_SECURE); 1752 #else 1753 cm_prepare_el3_exit(NON_SECURE); 1754 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1755 1756 if (is_feat_amu_supported()) { 1757 cm_sysregs_context_restore_amu(NON_SECURE); 1758 } 1759 } 1760 1761 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1762 /******************************************************************************* 1763 * The next set of six functions are used by runtime services to save and restore 1764 * EL1 context on the 'cpu_context' structure for the specified security state. 1765 ******************************************************************************/ 1766 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1767 { 1768 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1769 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1770 1771 #if (!ERRATA_SPECULATIVE_AT) 1772 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1773 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1774 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1775 1776 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1777 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1778 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1779 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1780 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1781 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1782 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1783 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1784 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1785 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1786 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1787 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1788 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1789 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1790 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1791 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1792 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1793 1794 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1795 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1796 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1797 1798 if (CTX_INCLUDE_AARCH32_REGS) { 1799 /* Save Aarch32 registers */ 1800 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1801 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1802 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1803 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1804 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1805 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1806 } 1807 1808 /* Save counter-timer kernel control register */ 1809 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1810 #if NS_TIMER_SWITCH 1811 /* Save NS Timer registers */ 1812 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1813 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1814 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1815 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1816 #endif 1817 1818 if (is_feat_mte2_supported()) { 1819 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1820 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1821 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1822 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1823 } 1824 1825 if (is_feat_ras_supported()) { 1826 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1827 } 1828 1829 if (is_feat_s1pie_supported()) { 1830 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1831 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1832 } 1833 1834 if (is_feat_s1poe_supported()) { 1835 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1836 } 1837 1838 if (is_feat_s2poe_supported()) { 1839 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1840 } 1841 1842 if (is_feat_tcr2_supported()) { 1843 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1844 } 1845 1846 if (is_feat_trf_supported()) { 1847 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1848 } 1849 1850 if (is_feat_csv2_2_supported()) { 1851 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1852 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1853 } 1854 1855 if (is_feat_gcs_supported()) { 1856 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1857 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1858 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1859 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1860 } 1861 1862 if (is_feat_the_supported()) { 1863 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1864 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1865 } 1866 1867 if (is_feat_sctlr2_supported()) { 1868 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1869 } 1870 1871 if (is_feat_ls64_accdata_supported()) { 1872 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1873 } 1874 } 1875 1876 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1877 { 1878 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1879 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1880 1881 #if (!ERRATA_SPECULATIVE_AT) 1882 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1883 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1884 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1885 1886 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1887 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1888 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1889 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1890 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1891 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1892 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1893 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1894 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1895 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1896 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1897 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1898 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1899 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1900 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1901 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1902 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1903 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1904 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1905 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1906 1907 if (CTX_INCLUDE_AARCH32_REGS) { 1908 /* Restore Aarch32 registers */ 1909 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1910 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1911 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1912 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1913 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1914 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1915 } 1916 1917 /* Restore counter-timer kernel control register */ 1918 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1919 #if NS_TIMER_SWITCH 1920 /* Restore NS Timer registers */ 1921 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1922 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1923 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1924 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1925 #endif 1926 1927 if (is_feat_mte2_supported()) { 1928 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1929 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1930 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1931 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1932 } 1933 1934 if (is_feat_ras_supported()) { 1935 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1936 } 1937 1938 if (is_feat_s1pie_supported()) { 1939 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1940 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1941 } 1942 1943 if (is_feat_s1poe_supported()) { 1944 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1945 } 1946 1947 if (is_feat_s2poe_supported()) { 1948 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1949 } 1950 1951 if (is_feat_tcr2_supported()) { 1952 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1953 } 1954 1955 if (is_feat_trf_supported()) { 1956 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1957 } 1958 1959 if (is_feat_csv2_2_supported()) { 1960 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1961 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1962 } 1963 1964 if (is_feat_gcs_supported()) { 1965 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1966 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1967 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1968 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1969 } 1970 1971 if (is_feat_the_supported()) { 1972 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1973 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1974 } 1975 1976 if (is_feat_sctlr2_supported()) { 1977 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1978 } 1979 1980 if (is_feat_ls64_accdata_supported()) { 1981 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1982 } 1983 } 1984 1985 /******************************************************************************* 1986 * The next couple of functions are used by runtime services to save and restore 1987 * EL1 context on the 'cpu_context' structure for the specified security state. 1988 ******************************************************************************/ 1989 void cm_el1_sysregs_context_save(uint32_t security_state) 1990 { 1991 cpu_context_t *ctx; 1992 1993 ctx = cm_get_context(security_state); 1994 assert(ctx != NULL); 1995 1996 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1997 1998 #if IMAGE_BL31 1999 if (is_feat_amu_supported()) { 2000 cm_sysregs_context_save_amu(security_state); 2001 } 2002 2003 if (security_state == SECURE) { 2004 PUBLISH_EVENT(cm_exited_secure_world); 2005 } else { 2006 PUBLISH_EVENT(cm_exited_normal_world); 2007 } 2008 #endif 2009 } 2010 2011 void cm_el1_sysregs_context_restore(uint32_t security_state) 2012 { 2013 cpu_context_t *ctx; 2014 2015 ctx = cm_get_context(security_state); 2016 assert(ctx != NULL); 2017 2018 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 2019 2020 #if IMAGE_BL31 2021 if (is_feat_amu_supported()) { 2022 cm_sysregs_context_restore_amu(security_state); 2023 } 2024 2025 if (security_state == SECURE) { 2026 PUBLISH_EVENT(cm_entering_secure_world); 2027 } else { 2028 PUBLISH_EVENT(cm_entering_normal_world); 2029 } 2030 #endif 2031 } 2032 2033 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 2034 2035 /******************************************************************************* 2036 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 2037 * given security state with the given entrypoint 2038 ******************************************************************************/ 2039 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 2040 { 2041 cpu_context_t *ctx; 2042 el3_state_t *state; 2043 2044 ctx = cm_get_context(security_state); 2045 assert(ctx != NULL); 2046 2047 /* Populate EL3 state so that ERET jumps to the correct entry */ 2048 state = get_el3state_ctx(ctx); 2049 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2050 } 2051 2052 /******************************************************************************* 2053 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 2054 * pertaining to the given security state 2055 ******************************************************************************/ 2056 void cm_set_elr_spsr_el3(uint32_t security_state, 2057 uintptr_t entrypoint, uint32_t spsr) 2058 { 2059 cpu_context_t *ctx; 2060 el3_state_t *state; 2061 2062 ctx = cm_get_context(security_state); 2063 assert(ctx != NULL); 2064 2065 /* Populate EL3 state so that ERET jumps to the correct entry */ 2066 state = get_el3state_ctx(ctx); 2067 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 2068 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 2069 } 2070 2071 /******************************************************************************* 2072 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 2073 * pertaining to the given security state using the value and bit position 2074 * specified in the parameters. It preserves all other bits. 2075 ******************************************************************************/ 2076 void cm_write_scr_el3_bit(uint32_t security_state, 2077 uint32_t bit_pos, 2078 uint32_t value) 2079 { 2080 cpu_context_t *ctx; 2081 el3_state_t *state; 2082 u_register_t scr_el3; 2083 2084 ctx = cm_get_context(security_state); 2085 assert(ctx != NULL); 2086 2087 /* Ensure that the bit position is a valid one */ 2088 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 2089 2090 /* Ensure that the 'value' is only a bit wide */ 2091 assert(value <= 1U); 2092 2093 /* 2094 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2095 * and set it to its new value. 2096 */ 2097 state = get_el3state_ctx(ctx); 2098 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2099 scr_el3 &= ~(1UL << bit_pos); 2100 scr_el3 |= (u_register_t)value << bit_pos; 2101 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2102 } 2103 2104 /******************************************************************************* 2105 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2106 * given security state. 2107 ******************************************************************************/ 2108 u_register_t cm_get_scr_el3(uint32_t security_state) 2109 { 2110 const cpu_context_t *ctx; 2111 const el3_state_t *state; 2112 2113 ctx = cm_get_context(security_state); 2114 assert(ctx != NULL); 2115 2116 /* Populate EL3 state so that ERET jumps to the correct entry */ 2117 state = get_el3state_ctx(ctx); 2118 return read_ctx_reg(state, CTX_SCR_EL3); 2119 } 2120 2121 /******************************************************************************* 2122 * This function is used to program the context that's used for exception 2123 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2124 * the required security state 2125 ******************************************************************************/ 2126 void cm_set_next_eret_context(uint32_t security_state) 2127 { 2128 cpu_context_t *ctx; 2129 2130 ctx = cm_get_context(security_state); 2131 assert(ctx != NULL); 2132 2133 cm_set_next_context(ctx); 2134 } 2135