1 /* 2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/fdt_wrappers.h> 10 #include <common/runtime_svc.h> 11 #include <libfdt.h> 12 #include <smccc_helpers.h> 13 14 /* default platform version is 0.0 */ 15 static int platform_version_major; 16 static int platform_version_minor; 17 18 #define SMC_FASTCALL 0x80000000 19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000) 20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000) 21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n)) 22 23 /* 24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform 25 * which uses SoC present in QEMU. And they can change on their own while we 26 * need version of whole 'virtual hardware platform'. 27 */ 28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1) 29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100) 30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101) 31 32 static uint64_t gic_its_addr; 33 34 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base); 35 uintptr_t sbsa_get_gicd(void); 36 uintptr_t sbsa_get_gicr(void); 37 38 void read_platform_config_from_dt(void *dtb) 39 { 40 int node; 41 const fdt64_t *data; 42 int err; 43 uintptr_t gicd_base; 44 uintptr_t gicr_base; 45 46 /* 47 * QEMU gives us this DeviceTree node: 48 * 49 * intc { 50 * reg = < 0x00 0x40060000 0x00 0x10000 51 * 0x00 0x40080000 0x00 0x4000000>; 52 * its { 53 * reg = <0x00 0x44081000 0x00 0x20000>; 54 * }; 55 * }; 56 */ 57 node = fdt_path_offset(dtb, "/intc"); 58 if (node < 0) { 59 return; 60 } 61 62 data = fdt_getprop(dtb, node, "reg", NULL); 63 if (data == NULL) { 64 return; 65 } 66 67 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL); 68 if (err < 0) { 69 ERROR("Failed to read GICD reg property of GIC node\n"); 70 return; 71 } 72 INFO("GICD base = 0x%lx\n", gicd_base); 73 74 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL); 75 if (err < 0) { 76 ERROR("Failed to read GICR reg property of GIC node\n"); 77 return; 78 } 79 INFO("GICR base = 0x%lx\n", gicr_base); 80 81 sbsa_set_gic_bases(gicd_base, gicr_base); 82 83 node = fdt_path_offset(dtb, "/intc/its"); 84 if (node < 0) { 85 return; 86 } 87 88 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL); 89 if (err < 0) { 90 ERROR("Failed to read GICI reg property of GIC node\n"); 91 return; 92 } 93 INFO("GICI base = 0x%lx\n", gic_its_addr); 94 } 95 96 void read_platform_version(void *dtb) 97 { 98 int node; 99 100 node = fdt_path_offset(dtb, "/"); 101 if (node >= 0) { 102 platform_version_major = fdt32_ld(fdt_getprop(dtb, node, 103 "machine-version-major", NULL)); 104 platform_version_minor = fdt32_ld(fdt_getprop(dtb, node, 105 "machine-version-minor", NULL)); 106 } 107 } 108 109 void sip_svc_init(void) 110 { 111 /* Read DeviceTree data before MMU is enabled */ 112 113 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 114 int err; 115 116 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE); 117 if (err < 0) { 118 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err); 119 return; 120 } 121 122 err = fdt_check_header(dtb); 123 if (err < 0) { 124 ERROR("Invalid DTB file passed\n"); 125 return; 126 } 127 128 read_platform_version(dtb); 129 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor); 130 131 read_platform_config_from_dt(dtb); 132 } 133 134 /* 135 * This function is responsible for handling all SiP calls from the NS world 136 */ 137 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid, 138 u_register_t x1, 139 u_register_t x2, 140 u_register_t x3, 141 u_register_t x4, 142 void *cookie, 143 void *handle, 144 u_register_t flags) 145 { 146 uint32_t ns; 147 148 /* Determine which security state this SMC originated from */ 149 ns = is_caller_non_secure(flags); 150 if (!ns) { 151 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid); 152 SMC_RET1(handle, SMC_UNK); 153 } 154 155 switch (smc_fid) { 156 case SIP_SVC_VERSION: 157 INFO("Platform version requested\n"); 158 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor); 159 160 case SIP_SVC_GET_GIC: 161 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr()); 162 163 case SIP_SVC_GET_GIC_ITS: 164 SMC_RET2(handle, NULL, gic_its_addr); 165 166 default: 167 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid, 168 smc_fid - SIP_FUNCTION); 169 SMC_RET1(handle, SMC_UNK); 170 } 171 } 172 173 int sbsa_sip_smc_setup(void) 174 { 175 return 0; 176 } 177 178 /* Define a runtime service descriptor for fast SMC calls */ 179 DECLARE_RT_SVC( 180 sbsa_sip_svc, 181 OEN_SIP_START, 182 OEN_SIP_END, 183 SMC_TYPE_FAST, 184 sbsa_sip_smc_setup, 185 sbsa_sip_smc_handler 186 ); 187