1 /* 2 * Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <lib/cassert.h> 12 #include <lib/el3_runtime/pubsub.h> 13 #include <lib/extensions/sve.h> 14 15 CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long); 16 CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short); 17 CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule); 18 19 /* 20 * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 21 * VECTOR_SIZE = (LEN+1) * 128 22 */ 23 #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 24 25 void sve_enable(cpu_context_t *context) 26 { 27 u_register_t cptr_el3; 28 29 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); 30 31 /* Enable access to SVE functionality for all ELs. */ 32 cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 33 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); 34 35 /* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */ 36 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, 37 (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN))); 38 } 39 40 void sve_init_el2_unused(void) 41 { 42 /* 43 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced 44 * SIMD and floating-point functionality from both Execution states do 45 * not trap to EL2. 46 */ 47 write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT); 48 } 49 50 void sve_disable(cpu_context_t *context) 51 { 52 u_register_t reg; 53 el3_state_t *state; 54 55 /* Get the context state. */ 56 state = get_el3state_ctx(context); 57 58 /* Disable SVE and FPU since they share registers. */ 59 reg = read_ctx_reg(state, CTX_CPTR_EL3); 60 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 61 reg |= TFP_BIT; /* Trap FPU/SIMD */ 62 write_ctx_reg(state, CTX_CPTR_EL3, reg); 63 } 64