core: thread_mask/unmask_exceptions() instead of read/write_daif

This change does not modify the core behavior, only update
core_mmu_set_user_map() to use generic exception masking routines.

Signed

core: thread_mask/unmask_exceptions() instead of read/write_daif

This change does not modify the core behavior, only update
core_mmu_set_user_map() to use generic exception masking routines.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: lpae: mask exceptions during core_mmu_find_table()

core_mmu_find_table() calls get_core_pos() so it should mask interrupts
to avoid being re-scheduled to another core.

Signed-off-by: Jerome F

core: lpae: mask exceptions during core_mmu_find_table()

core_mmu_find_table() calls get_core_pos() so it should mask interrupts
to avoid being re-scheduled to another core.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread: fix exception return

Fixes exception return from FIQ and SVC handlers to not return via
abort mode as we under some circumstances may return to abort mode.

Fixes: 5b8a58b415da ("core:

core: thread: fix exception return

Fixes exception return from FIQ and SVC handlers to not return via
abort mode as we under some circumstances may return to abort mode.

Fixes: 5b8a58b415da ("core: thread: fix exception return")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread_a64.S: fix gcc 4.9 compile error

Fixes compile errors
out/arm-plat-hikey/core/arch/arm/kernel/thread_a64.o: In function `el0_sync_abort':
/home/bla/optee_os/core/arch/arm/kernel/thread_

core: thread_a64.S: fix gcc 4.9 compile error

Fixes compile errors
out/arm-plat-hikey/core/arch/arm/kernel/thread_a64.o: In function `el0_sync_abort':
/home/bla/optee_os/core/arch/arm/kernel/thread_a64.S:778:(.text.el0_sync_abort+0xf4): relocation truncated to fit: R_AARCH64_TSTBR14 against `.text.thread_vect_table'
out/arm-plat-hikey/core/arch/arm/kernel/thread_a64.o: In function `elx_fiq':
/home/bla/optee_os/core/arch/arm/kernel/thread_a64.S:949:(.text.elx_fiq+0x9c): relocation truncated to fit: R_AARCH64_TSTBR14 against `.text.thread_vect_table'
make: *** [out/arm-plat-hikey/core/tee.elf] Error 1
experienced with some gcc 4.9 compiler

Fixes: https://github.com/OP-TEE/optee_os/issues/2067
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Victor Chong <victor.chong@linaro.org> (hikey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: pl310: fix cache sync

According to PL310 TRM:
Atomic operations:
The following are atomic operations:
Clean Line by PA or by Set/Way
Invalidate Line by PA
Clean and Invalidate Line

arm: pl310: fix cache sync

According to PL310 TRM:
Atomic operations:
The following are atomic operations:
Clean Line by PA or by Set/Way
Invalidate Line by PA
Clean and Invalidate Line by PA or by Set/Way
Cache Sync.
These operations stall the slave ports until they are complete.
When these registers are read, bit [0], the C flag, indicates that
a background operation is in progress. When written, bit 0 must be
zero.

So write 1 to sync register is not correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: crypto: default enable HWSUPP_PMULT_64 with CRYPTO_WITH_CE

64-bit polynomial multiply is defined in the ARMv8.0 Cryptographic
Extension instructions together with other instructions like AES*

core: crypto: default enable HWSUPP_PMULT_64 with CRYPTO_WITH_CE

64-bit polynomial multiply is defined in the ARMv8.0 Cryptographic
Extension instructions together with other instructions like AES*
and SHA1*. Therefore, it is reasonable to enable CFG_HWSUPP_PMULT_64
when CFG_CRYPTO_WITH_CE is enabled. Platforms can always override this
value if need be.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto: rename CFG_HWSUPP_PMULL to CFG_HWSUPP_PMULT_64

CFG_HWSUPP_PMULL is used to determine whether the CPU supports long
polynomial multiplies of 64-bit values, which means:
- for AArch64: P

core: crypto: rename CFG_HWSUPP_PMULL to CFG_HWSUPP_PMULT_64

CFG_HWSUPP_PMULL is used to determine whether the CPU supports long
polynomial multiplies of 64-bit values, which means:
- for AArch64: PMULL and PMULL2 with the 1Q arrangement specifier
- for AArch32: VMULL.P64
Otherwise, 8-bit polynomial multiplication is used instead.

Therefore, CFG_HWSUPP_PMULT_64 is a better name because it does not
seem to imply Aarch64 (no PMULL) and clearly states the 64-bit size.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: tee_svc_cryp.c: remove final ctx management

Removes the final remains of the crypo ctx management in tee_svc_cryp.c.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by:

core: tee_svc_cryp.c: remove final ctx management

Removes the final remains of the crypo ctx management in tee_svc_cryp.c.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto.h manages authenc context memory

To ease integration with other crypto libraries change the authenc context
interface in crypto.h to manage the memory used for the authenc context.

Rev

core: crypto.h manages authenc context memory

To ease integration with other crypto libraries change the authenc context
interface in crypto.h to manage the memory used for the authenc context.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto.h manages cipher context memory

To ease integration with other crypto libraries change the cipher context
interface in crypto.h to manage the memory used for the cipher context.

Review

core: crypto.h manages cipher context memory

To ease integration with other crypto libraries change the cipher context
interface in crypto.h to manage the memory used for the cipher context.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto.h manages mac context memory

To ease integration with other crypto libraries change the mac context
interface in crypto.h to manage the memory used for the mac context.

Reviewed-by: Je

core: crypto.h manages mac context memory

To ease integration with other crypto libraries change the mac context
interface in crypto.h to manage the memory used for the mac context.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto.h manages hash context memory

To ease integration with other crypto libraries change the hash context
interface in crypto.h to manage the memory used for the hash context.

Reviewed-by:

core: crypto.h manages hash context memory

To ease integration with other crypto libraries change the hash context
interface in crypto.h to manage the memory used for the hash context.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words

Remove 'All rights reserved' from Linaro files

The text 'All rights reserved' is useless [1]. The Free Software
Foundation's REUSE Initiative best practices document [2] does not
contain these words. Therefore, we can safely remove the text from the
files that are owned by Linaro.

Generated by:
spdxify.py --linaro-only --strip-arr optee_os/

Link: [1] https://en.wikipedia.org/wiki/All_rights_reserved
Link: [2] https://reuse.software/practices/
Link: [3] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.p

Remove license notice from Linaro files

Now that we have added SPDX identifiers, we can safely remove the
verbose license text from the files that are owned by Linaro.

Generated by [1]:
spdxify.py --linaro-only --strip-license-text optee_os/

Link: [1] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] wa

Add SPDX license identifiers

Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.

Generated by [2]:
spdxify.py --add-spdx optee_os/

The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.

Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Reformat copyright/license header in files with an SPDX ID

Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.

[1] documentation/

Reformat copyright/license header in files with an SPDX ID

Some files were committed with an SPDX license identifier before the
rules were defined [1]. Reformat them accordingly.

[1] documentation/copyright_and_license_headers.rst

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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Document copyright and license header rules

Add a file to explain how the copyright and license information should
be described in source files. We are essentially following the Linux
kernel guideli

Document copyright and license header rules

Add a file to explain how the copyright and license information should
be described in source files. We are essentially following the Linux
kernel guidelines which are currently being discussed [1].

[1] https://patchwork.kernel.org/patch/10091607/

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: lpae: zero initialize all l1 tables

Fixes: 4cc2823eb25c ("core: user mode translation table")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.fo

core: lpae: zero initialize all l1 tables

Fixes: 4cc2823eb25c ("core: user mode translation table")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Hikey)

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documentation: mmu and switch to/from user space

This only describes the already documented legacy ARMv7 (short) table
format.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by

documentation: mmu and switch to/from user space

This only describes the already documented legacy ARMv7 (short) table
format.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename mattr_uflags_to_str()

Renames mattr_uflags_to_str() to mattr_perm_to_str() and report all
permission bits using a 7 bytes long string instead.

This allows observing the permissions of

core: rename mattr_uflags_to_str()

Renames mattr_uflags_to_str() to mattr_perm_to_str() and report all
permission bits using a 7 bytes long string instead.

This allows observing the permissions of the minimal kernel mapping
added to the user space context.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make all mapping non-global

Makes all mapping non-global to avoid the otherwise required tlb
invalidation when switching to user mode.

This change makes the fix for CVE-2017-5754 complete.

R

core: make all mapping non-global

Makes all mapping non-global to avoid the otherwise required tlb
invalidation when switching to user mode.

This change makes the fix for CVE-2017-5754 complete.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: use minimal kernel map in user space

Adds a trampoline in the exception vector to switch to a minimal kernel
map when in user mode. When returning to kernel mode the full kernel
mode map is re

core: use minimal kernel map in user space

Adds a trampoline in the exception vector to switch to a minimal kernel
map when in user mode. When returning to kernel mode the full kernel
mode map is restored.

Arm32 tries to mimic the arm64 exception model somewhat by letting each
exception handler run with disabled asynchronous aborts, irq and fiq.

Form arm32 accesses to the cpus thread_core_local is only done via the
stack pointer in abort mode. Entry of user mode is only done via abort
mode, that means that the abort mode spsr register carries the new cpsr.
Care is taken to have all exceptions disabled while using abort mode.

ASIDs are paired with a user mode ASID with lowest bit sset and a
kernel mode ASID with the lowest bit cleared.

ASID 0 is reserved for kernel mode use when there's no user mode mapping
active.

With this change an active used mode mapping while in kernel mode uses
(asid | 0), and while in user mode (asid | 1). The switch is done via
the trampoline in the vector.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: thread_a32.S: move intr handler macros

Moves the interrupt handler macros closer to the vector.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jero

core: thread_a32.S: move intr handler macros

Moves the interrupt handler macros closer to the vector.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: exception handlers in one section

Moves all exception handlers into the section of the vector,
.text.thread_vect_table. This makes it possible to later map just the
exception vector and

core: arm32: exception handlers in one section

Moves all exception handlers into the section of the vector,
.text.thread_vect_table. This makes it possible to later map just the
exception vector and the closest associated code while in user mode.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: user mode translation table

Adds a second translation table to be used while in user mode containing
user mode mapping and a minimal kernel mapping.

Reviewed-by: Etienne Carriere <etienne.car

core: user mode translation table

Adds a second translation table to be used while in user mode containing
user mode mapping and a minimal kernel mapping.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Andrew Davis <andrew.davis@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...