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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 144) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/microchip/
H A Dddr2.c106 hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2; in host_load_cmd()
139 writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
140 REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) | in ddr2_ctrl_init()
151 wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL), in ddr2_ctrl_init()
152 DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL; in ddr2_ctrl_init()
154 wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL; in ddr2_ctrl_init()
155 rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL), in ddr2_ctrl_init()
156 DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2; in ddr2_ctrl_init()
157 ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL), in ddr2_ctrl_init()
158 DIV_ROUND_UP(T_RRD_TCK, 2)) - 1; in ddr2_ctrl_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dddr.c1001 trfc = DIV_ROUND_UP(130000, clkper) - 1; in mx6_lpddr2_cfg()
1002 txsr = DIV_ROUND_UP(140000, clkper) - 1; in mx6_lpddr2_cfg()
1005 trfc = DIV_ROUND_UP(210000, clkper) - 1; in mx6_lpddr2_cfg()
1006 txsr = DIV_ROUND_UP(220000, clkper) - 1; in mx6_lpddr2_cfg()
1018 txp = DIV_ROUND_UP(7500, clkper) - 1; in mx6_lpddr2_cfg()
1021 tfaw = DIV_ROUND_UP(60000, clkper) - 1; in mx6_lpddr2_cfg()
1023 tfaw = DIV_ROUND_UP(50000, clkper) - 1; in mx6_lpddr2_cfg()
1024 trrd = DIV_ROUND_UP(10000, clkper) - 1; in mx6_lpddr2_cfg()
1027 tcksre = DIV_ROUND_UP(15000, clkper); in mx6_lpddr2_cfg()
1029 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c233 div = DIV_ROUND_UP(priv->v0pll_hz, new_rate); in rk3506_armclk_set_rate()
237 div = DIV_ROUND_UP(priv->v1pll_hz, new_rate); in rk3506_armclk_set_rate()
241 div = DIV_ROUND_UP(priv->gpll_hz, new_rate); in rk3506_armclk_set_rate()
312 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3506_pll_div_set_rate()
318 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_pll_div_set_rate()
324 div = DIV_ROUND_UP(priv->v0pll_hz, rate); in rk3506_pll_div_set_rate()
330 div = DIV_ROUND_UP(priv->v1pll_hz, rate); in rk3506_pll_div_set_rate()
388 div = DIV_ROUND_UP(priv->v0pll_div_hz, rate); in rk3506_bus_set_rate()
391 div = DIV_ROUND_UP(priv->v1pll_div_hz, rate); in rk3506_bus_set_rate()
394 div = DIV_ROUND_UP(priv->gpll_div_hz, rate); in rk3506_bus_set_rate()
[all …]
H A Dclk_rk3562.c244 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_bus_set_rate()
247 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_bus_set_rate()
318 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_peri_set_rate()
321 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_peri_set_rate()
412 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_i2c_set_rate()
532 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
590 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3562_uart_set_rate()
594 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3562_uart_set_rate()
689 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_pwm_set_rate()
789 div = DIV_ROUND_UP(200 * MHz, rate); in rk3562_spi_set_rate()
[all …]
H A Dclk_rv1108.c158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
290 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
320 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
372 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
388 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
403 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
[all …]
H A Dclk_rk3576.c227 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_bus_set_clk()
230 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_bus_set_clk()
344 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
347 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
360 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3576_top_set_clk()
363 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_top_set_clk()
727 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3576_adc_set_clk()
737 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3576_adc_set_clk()
749 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3576_adc_set_clk()
876 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3576_mmc_set_clk()
[all …]
H A Dclk_rk1808.c139 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_i2c_set_clk()
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
251 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk1808_mmc_set_clk()
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
310 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_saradc_set_clk()
353 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_pwm_set_clk()
399 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in rk1808_tsadc_set_clk()
441 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_spi_set_clk()
522 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk1808_vop_set_clk()
536 DIV_ROUND_UP(rk1808_vop_get_clk(priv, ACLK_VOPRAW), hz); in rk1808_vop_set_clk()
[all …]
H A Dclk_rv1126.c241 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_i2c_set_pmuclk()
303 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
321 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pwm_set_pmuclk()
355 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_spi_set_pmuclk()
383 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdpmu_set_pmuclk()
611 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdcore_set_clk()
676 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
679 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rv1126_pdbus_set_clk()
689 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
698 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rv1126_pdbus_set_clk()
[all …]
H A Dclk_rk3328.c269 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
293 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2phy_src_set_clk()
365 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk3328_mmc_set_clk()
369 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
455 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_saradc_set_clk()
482 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3328_tsadc_set_clk()
530 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
550 src_clk_div = DIV_ROUND_UP(rk3328_vop_get_clk(priv, in rk3328_vop_set_clk()
565 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz); in rk3328_vop_set_clk()
567 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3328_vop_set_clk()
[all …]
H A Dclk_px30.c124 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz); in pll_clk_set_by_auto()
126 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_clk_set_by_auto()
127 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_clk_set_by_auto()
332 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_i2c_set_clk()
538 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
603 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in px30_mmc_set_clk()
607 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in px30_mmc_set_clk()
641 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_sfc_set_clk()
677 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in px30_pwm_set_clk()
719 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz); in px30_saradc_set_clk()
[all …]
H A Dclk_rk3288.c371 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
373 *ext_div = DIV_ROUND_UP(PLL_LIMIT_FREQ, freq_hz); in pll_para_config()
374 no = DIV_ROUND_UP(no, *ext_div); in pll_para_config()
388 no = DIV_ROUND_UP(no, 2) * 2; in pll_para_config()
461 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
512 lcdc_div = DIV_ROUND_UP(gpll_rate, in rockchip_vop_set_clk()
516 lcdc_div = DIV_ROUND_UP(npll_rate, in rockchip_vop_set_clk()
550 lcdc_div = DIV_ROUND_UP(gpll_rate, in rockchip_vop_set_clk()
554 lcdc_div = DIV_ROUND_UP(npll_rate, in rockchip_vop_set_clk()
563 lcdc_div = DIV_ROUND_UP(gpll_rate, rate_hz); in rockchip_vop_set_clk()
[all …]
H A Dclk_rk322x.c203 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
225 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rk322x_mmc_set_clk()
228 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rk322x_mmc_set_clk()
315 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_bus_set_clk()
323 src_clk_div = DIV_ROUND_UP(rk322x_bus_get_clk(priv, in rk322x_bus_set_clk()
332 src_clk_div = DIV_ROUND_UP(rk322x_bus_get_clk(priv, in rk322x_bus_set_clk()
388 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_peri_set_clk()
396 src_clk_div = DIV_ROUND_UP(rk322x_peri_get_clk(priv, in rk322x_peri_set_clk()
405 src_clk_div = DIV_ROUND_UP(rk322x_peri_get_clk(priv, in rk322x_peri_set_clk()
438 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk322x_spi_set_clk()
[all …]
H A Dclk_rk3128.c185 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, freq); in rockchip_mmc_set_clk()
188 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
266 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_peri_set_clk()
279 src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv, in rk3128_peri_set_clk()
288 src_clk_div = DIV_ROUND_UP(rk3128_peri_get_clk(priv, in rk3128_peri_set_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_bus_set_clk()
349 src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv, in rk3128_bus_set_clk()
358 src_clk_div = DIV_ROUND_UP(rk3128_bus_get_clk(priv, in rk3128_bus_set_clk()
391 div = DIV_ROUND_UP(priv->gpll_hz, hz); in rk3128_spi_set_clk()
418 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rk3128_saradc_set_clk()
[all …]
H A Dclk_rk3588.c338 src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_top_set_clk()
341 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
352 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_top_set_clk()
694 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
704 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
717 src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_adc_set_clk()
727 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_adc_set_clk()
823 div = DIV_ROUND_UP(OSC_HZ, rate); in rk3588_mmc_set_clk()
826 div = DIV_ROUND_UP(priv->cpll_hz, rate); in rk3588_mmc_set_clk()
829 div = DIV_ROUND_UP(priv->gpll_hz, rate); in rk3588_mmc_set_clk()
[all …]
H A Dclk_rk3036.c186 nandc_div = DIV_ROUND_UP(GPLL_HZ, 150 * 1000000); in rkclk_init()
287 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); in rockchip_mmc_set_clk()
290 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); in rockchip_mmc_set_clk()
352 div = DIV_ROUND_UP(clk_general_rate, hz); in rk3036_spi_set_clk()
382 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); in rockchip_dclk_lcdc_set_clk()
414 src_clk_div = DIV_ROUND_UP(clk_general_rate, freq); in rockchip_aclk_lcdc_set_clk()
459 src_clk_div = DIV_ROUND_UP(clk_general_rate, hz); in rk3036_peri_set_clk()
467 src_clk_div = DIV_ROUND_UP(rk3036_peri_get_clk(priv, in rk3036_peri_set_clk()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_dsc.c261 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()
265 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
270 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()
274 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()
325 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), in drm_dsc_compute_rc_parameters()
334 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
365 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * in drm_dsc_compute_rc_parameters()
369 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); in drm_dsc_compute_rc_parameters()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Drk_meta.c138 DIV_ROUND_UP(MAX_META_SEGMENT_SIZE, info->bl_len), data) in spl_load_meta()
139 != DIV_ROUND_UP(MAX_META_SEGMENT_SIZE, info->bl_len)) { in spl_load_meta()
158 DIV_ROUND_UP(meta_iq_item_size, info->bl_len), in spl_load_meta()
160 != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) { in spl_load_meta()
178 DIV_ROUND_UP(meta_iq_item_size, info->bl_len), in spl_load_meta()
180 != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) { in spl_load_meta()
H A Duimage.c26 blknum = DIV_ROUND_UP(size, blksz) + !!unused; in uimage_load_one()
113 blknum = DIV_ROUND_UP(image_get_image_size(hdr), dev_desc->blksz); in uimage_load_bootables()
142 blknum = DIV_ROUND_UP(size, blksz); in uimage_sysmem_reserve_each()
150 blknum = DIV_ROUND_UP(size, blksz); in uimage_sysmem_reserve_each()
157 blknum = DIV_ROUND_UP(size, blksz); in uimage_sysmem_reserve_each()
/rk3399_rockchip-uboot/drivers/i2c/
H A Drk_i2c.c111 *divh = DIV_ROUND_UP(div, 2); in rk_i2c_get_div()
127 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; in rk_i2c_set_clk()
166 i2c_rate = DIV_ROUND_UP(i2c_rate, 1000); in rk_i2c_adapter_clk()
167 speed = DIV_ROUND_UP(scl_rate, 1000); in rk_i2c_adapter_clk()
169 min_total_div = DIV_ROUND_UP(i2c_rate, speed * 8); in rk_i2c_adapter_clk()
172 min_high_div = DIV_ROUND_UP(i2c_rate * min_high_ns, 8 * 1000000); in rk_i2c_adapter_clk()
175 min_low_div = DIV_ROUND_UP(i2c_rate * min_low_ns, 8 * 1000000); in rk_i2c_adapter_clk()
187 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div, in rk_i2c_adapter_clk()
322 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); in rk_i2c_read()
402 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); in rk_i2c_write()
/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-gic.c42 uint32_t icfgr[DIV_ROUND_UP(1020, 16)];
43 uint32_t itargetsr[DIV_ROUND_UP(1020, 4)];
44 uint32_t ipriorityr[DIV_ROUND_UP(1020, 4)];
45 uint32_t igroupr[DIV_ROUND_UP(1020, 32)];
46 uint32_t ispendr[DIV_ROUND_UP(1020, 32)];
47 uint32_t isenabler[DIV_ROUND_UP(1020, 32)];
/rk3399_rockchip-uboot/tools/
H A Drknand.c13 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) macro
88 DIV_ROUND_UP(tplsplsize, RKNAND_SECT_LEN) * ninfo.itersize; in rknand_vrec_header()
/rk3399_rockchip-uboot/common/
H A Dimage-android.c132 *out_blk_offset = DIV_ROUND_UP(offset, desc->blksz); in android_image_init_resource()
228 DIV_ROUND_UP(hdr->kernel_size, 1024)); in android_image_get_kernel()
346 start, end, DIV_ROUND_UP(hdr->vendor_ramdisk_size, 1024)); in android_image_get_ramdisk()
352 start, end, DIV_ROUND_UP(hdr->ramdisk_size, 1024)); in android_image_get_ramdisk()
358 start, end, DIV_ROUND_UP(hdr->vendor_bootconfig_size, 1024)); in android_image_get_ramdisk()
387 hdr->second_addr, DIV_ROUND_UP(hdr->second_size, 1024)); in android_image_get_fdt()
444 blkcnt = DIV_ROUND_UP(hdr->kernel_size + pgsz, blksz); in image_load()
468 blkcnt = DIV_ROUND_UP(hdr->vendor_ramdisk_size, blksz); in image_load()
509 blkcnt = DIV_ROUND_UP(hdr->ramdisk_size, blksz); in image_load()
570 blkcnt = DIV_ROUND_UP(hdr->vendor_bootconfig_size, blksz); in image_load()
[all …]
/rk3399_rockchip-uboot/include/linux/
H A Ddelay.h21 udelay(DIV_ROUND_UP(nsec, 1000)); in ndelay()
/rk3399_rockchip-uboot/board/freescale/common/
H A Dvid.c152 voltage_read = DIV_ROUND_UP(voltage_read, 128); in read_voltage_from_IR()
251 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
253 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
392 vdd_target = DIV_ROUND_UP(vdd_target, 10); in adjust_vdd()
579 vdd_target = DIV_ROUND_UP(vdd_target, 10); in adjust_vdd()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dppa.c99 cnt = DIV_ROUND_UP(fdt_header_len, 512); in ppa_init()
125 cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); in ppa_init()
149 cnt = DIV_ROUND_UP(fw_length, 512); in ppa_init()

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