irq: gicv3: use cpu interface system registers for gicc read/write

RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e4

irq: gicv3: use cpu interface system registers for gicc read/write

RK3568 only support cpu interface system registers access.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: Ie89380e49ee61afe57560dcc4eba6233f2aca3f2

show more ...

irq: gicv3: Enables Group 1 interrupts for the current Security state

When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.

Signed-off-by: shengfei X

irq: gicv3: Enables Group 1 interrupts for the current Security state

When a CPU enters a low power state, the registers ICC_IGRPEN1_EL1 is lost.
It need to re-initialise.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I62d9eed2b29190134d95ebd153f21aa764c4ab3b

show more ...

irq: gicv2: fix GIC not response to USB OTG IRQ

It handles the issue when the bootflow without Miniloader,
i.e. Maskrom => Trust(optional) => U-Boot.

Change-Id: I445225d5cce9abd2117ef468f15774e3fa5

irq: gicv2: fix GIC not response to USB OTG IRQ

It handles the issue when the bootflow without Miniloader,
i.e. Maskrom => Trust(optional) => U-Boot.

Change-Id: I445225d5cce9abd2117ef468f15774e3fa57e16d
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...

irq: clean up code

Change-Id: I51c2713b7c42fa798fee6971a2c91d867042ef70
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: clean up code

- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;

Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by:

irq: clean up code

- using IRQ_X() to print message;
- update some comment;
- rename some function;
- add more strict irq sanity;

Change-Id: If5432818d4bc12fc1aa0b8aca6898bbf79dfa9fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...

irq: gic v2/v3: support set target cpu by mpidr dynamiclly

Change-Id: I4a45ad1d81ab9b2e8ae958e6307030200bb405f1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: clean up code

remove unused code and fix compile warning.

Change-Id: I912eff25bf60da925791b889f08e91d4fcb61893
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

irq: support irq suspend and resume

U-Boot will support cpu suspend/resume, cpu and logic may
lose power, this patch guarantees gic works normally.

Change-Id: I8ebee881fa27fea075502f962f9faabaa8264

irq: support irq suspend and resume

U-Boot will support cpu suspend/resume, cpu and logic may
lose power, this patch guarantees gic works normally.

Change-Id: I8ebee881fa27fea075502f962f9faabaa8264f67
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...

drivers: add irq interrupt framework support

This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.

The framework support gic i

drivers: add irq interrupt framework support

This patch add support for IRQ interrupt, FIQ not included.
It will be enabled when you select CONFIG_GICV2 or CONFIG_GICV3.

The framework support gic interrupt and gpio interrupt, relative APIs
are provided in: ./include/irq-platform.h

If you'd like to add a new platform support into interrupt framework,
please follow the steps:
1. add relative definitions in the file like other platforms:
./include/irq-platform.h

2. add GICD, GICC and GICR(for GICV3) base address definitions in the
rkxxx-common.h, they are needed in: arch/arm/cpu/armv8/start.S;

3. enable CONFIG_GICV2 or CONFIG_GICV3.

Notice:
1. the framework is initialize in function 'interrupt_init()' of
_sequence_r[]. So you should not request irqs too early.

2. IRQ stack size is configured by CONFIG_IRQ_STACK_SIZE, the default
value is 8KB when CONFIG_IRQ_STACK_SIZE is absent.

Change-Id: I3d9e29873c9d64cd28aabd13a61111438c5902b0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

show more ...