227 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_bus_set_clk()
230 			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_bus_set_clk()
344 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_top_set_clk()
347 			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_top_set_clk()
360 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_top_set_clk()
363 			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_top_set_clk()
727 			src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_adc_set_clk()
737 			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_adc_set_clk()
749 		src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_adc_set_clk()
876 			div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_mmc_set_clk()
879 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_mmc_set_clk()
882 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_mmc_set_clk()
898 			div = DIV_ROUND_UP(priv->spll_hz, rate);  in rk3576_mmc_set_clk()
901 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_mmc_set_clk()
1057 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1060 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1071 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1074 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1085 			div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1088 			div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_aclk_vop_set_clk()
1216 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1222 			div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, rate);  in rk3576_dclk_vop_set_clk()
1257 			div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_vop_set_clk()
1357 		div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_clk_csihost_set_clk()
1449 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1454 				div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ,  in rk3576_dclk_ebc_set_clk()
1497 				div = DIV_ROUND_UP(pll_rate, rate);  in rk3576_dclk_ebc_set_clk()
1535 				val = DIV_ROUND_UP(4, m);  in rk3576_dclk_ebc_set_clk()
1607 	div = DIV_ROUND_UP(priv->cpll_hz, rate);  in rk3576_gmac_set_clk()
1726 			val = DIV_ROUND_UP(4, m);  in rk3576_uart_frac_set_rate()
1843 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_uart_set_rate()
1846 		div = DIV_ROUND_UP(priv->gpll_hz, rate);  in rk3576_uart_set_rate()
1849 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0), rate);  in rk3576_uart_set_rate()
1852 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1), rate);  in rk3576_uart_set_rate()
1855 		div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2), rate);  in rk3576_uart_set_rate()
1858 		div = DIV_ROUND_UP(OSC_HZ, rate);  in rk3576_uart_set_rate()
2008 		div = DIV_ROUND_UP(p_rate, rate);  in rk3576_ref_clkout_set_clk()