139 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_i2c_set_clk()
247 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate);  in rk1808_mmc_set_clk()
251 		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);  in rk1808_mmc_set_clk()
285 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);  in rk1808_sfc_set_clk()
310 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in rk1808_saradc_set_clk()
353 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_pwm_set_clk()
399 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in rk1808_tsadc_set_clk()
441 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_spi_set_clk()
522 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_vop_set_clk()
536 			DIV_ROUND_UP(rk1808_vop_get_clk(priv, ACLK_VOPRAW), hz);  in rk1808_vop_set_clk()
546 		src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ, hz);  in rk1808_vop_set_clk()
566 			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, hz);  in rk1808_vop_set_clk()
569 			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_vop_set_clk()
572 			src_clk_div = DIV_ROUND_UP(RK1808_VOP_PLL_LIMIT_FREQ,  in rk1808_vop_set_clk()
616 	div = DIV_ROUND_UP(pll_rate, hz) - 1;  in rk1808_mac_set_clk()
684 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_crypto_set_clk()
754 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_bus_set_clk()
762 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_bus_set_clk()
770 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_bus_set_clk()
816 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in rk1808_peri_set_clk()
850 	src_clk_div = DIV_ROUND_UP(parent_hz, hz);  in rk1808_pclk_pmu_set_clk()