Lines Matching refs:DIV_ROUND_UP
158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
204 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; in rv1108_saradc_set_clk()
229 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio1_set_clk()
255 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_aclk_vio0_set_clk()
290 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; in rv1108_dclk_vop_set_clk()
320 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_bus_set_clk()
372 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_aclk_peri_set_clk()
388 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_hclk_peri_set_clk()
403 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1; in rv1108_pclk_peri_set_clk()
501 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), hz); in rv1108_spi_set_clk()
534 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate); in rv1108_mmc_set_clk()
548 div = DIV_ROUND_UP(pll_rate / 2, rate); in rv1108_mmc_set_clk()