124 	postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, rate_khz);  in pll_clk_set_by_auto()
126 		postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);  in pll_clk_set_by_auto()
127 		postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);  in pll_clk_set_by_auto()
332 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_i2c_set_clk()
538 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);  in px30_nandc_set_clk()
603 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate);  in px30_mmc_set_clk()
607 		src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);  in px30_mmc_set_clk()
641 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);  in px30_sfc_set_clk()
677 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_pwm_set_clk()
719 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_saradc_set_clk()
745 	src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_tsadc_set_clk()
782 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_spi_set_clk()
846 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_vop_set_clk()
855 			src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz);  in px30_vop_set_clk()
877 				src_clk_div = DIV_ROUND_UP(PX30_VOP_PLL_LIMIT, hz);  in px30_vop_set_clk()
942 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_bus_set_clk()
950 		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_bus_set_clk()
959 			DIV_ROUND_UP(px30_bus_get_clk(priv, ACLK_BUS_PRE), hz);  in px30_bus_set_clk()
1002 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_peri_set_clk()
1078 		div = DIV_ROUND_UP(parent, hz);  in px30_otp_set_clk()
1088 		div = DIV_ROUND_UP(OSC_HZ, hz);  in px30_otp_set_clk()
1094 		div = DIV_ROUND_UP(px30_otp_get_clk(priv, SCLK_OTP), hz);  in px30_otp_set_clk()
1136 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_crypto_set_clk()
1184 	div = DIV_ROUND_UP(pll_rate, hz) - 1;  in px30_mac_set_clk()
1752 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, hz);  in px30_pclk_pmu_set_pmuclk()
1793 	div = DIV_ROUND_UP(hz, priv->gpll_hz);  in px30_gpll_set_pmuclk()