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Searched refs:CPLL (Results 1 – 25 of 30) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dclk.h19 #define CPLL 8 macro
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3128.c85 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(8),
455 rockchip_pll_set_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_set_clk()
456 priv->cru, CPLL, src_clk_div * hz); in rk3128_vop_set_clk()
490 parent = rockchip_pll_get_rate(&rk3128_pll_clks[CPLL], in rk3128_vop_get_rate()
491 priv->cru, CPLL); in rk3128_vop_get_rate()
837 rockchip_pll_set_rate(&rk3128_pll_clks[CPLL], in rkclk_init()
838 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
H A Dclk_rk3328.c110 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3328_PLL_CON(16),
793 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_get_rate()
794 priv->cru, CPLL); in rk3328_clk_get_rate()
880 ret = rockchip_pll_set_rate(&rk3328_pll_clks[CPLL], in rk3328_clk_set_rate()
881 priv->cru, CPLL, rate); in rk3328_clk_set_rate()
1288 priv->cpll_hz = rockchip_pll_get_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1289 priv->cru, CPLL); in rkclk_init()
1304 rockchip_pll_set_rate(&rk3328_pll_clks[CPLL], in rkclk_init()
1305 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
H A Dclk_rk322x.c86 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK2928_PLL_CON(6),
649 ret = rockchip_pll_set_rate(&rk322x_pll_clks[CPLL], in rk322x_clk_set_rate()
650 priv->cru, CPLL, rate); in rk322x_clk_set_rate()
963 priv->cpll_hz = rockchip_pll_get_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
964 priv->cru, CPLL); in rkclk_init()
996 rockchip_pll_set_rate(&rk322x_pll_clks[CPLL], in rkclk_init()
997 priv->cru, CPLL, CPLL_HZ); in rkclk_init()
H A Dclk_rk1808.c84 [CPLL] = PLL(pll_rk3036, PLL_CPLL, RK1808_PLL_CON(16),
609 pll_rate = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_mac_set_clk()
610 priv->cru, CPLL); in rk1808_mac_set_clk()
1009 ret = rockchip_pll_set_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_set_rate()
1010 priv->cru, CPLL, rate); in rk1808_clk_set_rate()
1308 priv->cpll_hz = rockchip_pll_get_rate(&rk1808_pll_clks[CPLL], in rk1808_clk_probe()
1309 priv->cru, CPLL); in rk1808_clk_probe()
H A Dclk_rv1106.c43 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1106_PLL_CON(8),
1060 rate = rockchip_pll_get_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_get_rate()
1061 CPLL); in rv1106_clk_get_rate()
1161 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_set_rate()
1162 CPLL, rate); in rv1106_clk_set_rate()
1281 ret = rockchip_pll_set_rate(&rv1106_pll_clks[CPLL], priv->cru, in rv1106_clk_init()
1282 CPLL, CPLL_HZ); in rv1106_clk_init()
H A Dclk_rk3528.c69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
1350 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_get_rate()
1351 CPLL); in rk3528_clk_get_rate()
1469 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_set_rate()
1470 CPLL, rate); in rk3528_clk_set_rate()
1471 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], in rk3528_clk_set_rate()
1472 priv->cru, CPLL); in rk3528_clk_set_rate()
1943 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, in rk3528_clk_init()
1944 CPLL, CPLL_HZ); in rk3528_clk_init()
H A Dclk_rv1126b.c48 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126B_PERIPLL_CON(0),
1486 rate = rockchip_pll_get_rate(&rv1126b_pll_clks[CPLL], priv->cru, in rv1126b_clk_get_rate()
1487 CPLL); in rv1126b_clk_get_rate()
1618 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, in rv1126b_clk_set_rate()
1619 CPLL, rate); in rv1126b_clk_set_rate()
1844 priv->cpll_hz = rockchip_pll_get_rate(&rv1126b_pll_clks[CPLL], in rv1126b_clk_init()
1845 priv->cru, CPLL); in rv1126b_clk_init()
1847 ret = rockchip_pll_set_rate(&rv1126b_pll_clks[CPLL], priv->cru, in rv1126b_clk_init()
1848 CPLL, CPLL_HZ); in rv1126b_clk_init()
H A Dclk_rk3368.c321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
755 parent = rkclk_pll_get_rate(cru, CPLL); in rk3368_vop_get_clk()
794 if ((rkclk_pll_get_rate(cru, CPLL) % hz) == 0) { in rk3368_vop_set_clk()
795 lcdc_div = rkclk_pll_get_rate(cru, CPLL) / hz; in rk3368_vop_set_clk()
1278 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
1284 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
H A Dclk_rk3588.c60 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),
1572 rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_get_rate()
1573 CPLL); in rk3588_clk_get_rate()
1711 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_set_rate()
1712 CPLL, rate); in rk3588_clk_set_rate()
1713 priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], in rk3588_clk_set_rate()
1714 priv->cru, CPLL); in rk3588_clk_set_rate()
2072 ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru, in rk3588_clk_init()
2073 CPLL, CPLL_HZ); in rk3588_clk_init()
H A Dclk_rk3576.c75 [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
2083 rate = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], priv->cru, in rk3576_clk_get_rate()
2084 CPLL); in rk3576_clk_get_rate()
2237 ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru, in rk3576_clk_set_rate()
2238 CPLL, rate); in rk3576_clk_set_rate()
2239 priv->cpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], in rk3576_clk_set_rate()
2240 priv->cru, CPLL); in rk3576_clk_set_rate()
2521 ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru, in rk3576_clk_init()
2522 CPLL, CPLL_HZ); in rk3576_clk_init()
H A Dclk_rv1126.c64 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16),
1629 rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_get_rate()
1630 CPLL); in rv1126_clk_get_rate()
1751 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_set_rate()
1752 CPLL, rate); in rv1126_clk_set_rate()
2147 ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, in rv1126_clk_init()
2148 CPLL, CPLL_HZ); in rv1126_clk_init()
H A Dclk_px30.c823 parent = rkclk_pll_get_rate(&cru->pll[CPLL], &cru->mode, CPLL); in px30_vop_get_clk()
862 rkclk_set_pll(&cru->pll[CPLL], &cru->mode, CPLL, hz * src_clk_div); in px30_vop_set_clk()
1174 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1309 rate = px30_clk_get_pll_rate(priv, CPLL); in px30_clk_get_rate()
H A Dclk_rk3568.c72 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3568_PLL_CON(24),
2534 rate = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_get_rate()
2535 CPLL); in rk3568_clk_get_rate()
2717 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_set_rate()
2718 CPLL, rate); in rk3568_clk_set_rate()
2719 priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL], in rk3568_clk_set_rate()
2720 priv->cru, CPLL); in rk3568_clk_set_rate()
3268 ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru, in rk3568_clk_init()
3269 CPLL, CPLL_HZ); in rk3568_clk_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3128.h65 CPLL, enumerator
H A Dcru_rk3368.h17 CPLL, enumerator
H A Dcru_rk322x.h62 CPLL, enumerator
H A Dcru_rk3328.h60 CPLL, enumerator
H A Dcru_rv1106.h28 CPLL, enumerator
H A Dcru_rk1808.h22 CPLL, enumerator
H A Dcru_rv1126.h50 CPLL, enumerator
H A Dcru_px30.h29 CPLL, enumerator
H A Dcru_rk3528.h23 CPLL, enumerator
H A Dcru_rk3562.h28 CPLL, enumerator
H A Dcru_rv1126b.h25 CPLL, enumerator

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