1de4fa243SKever Yang /* 2de4fa243SKever Yang * Copyright (c) 2017 Rockchip Electronics Co., Ltd 3de4fa243SKever Yang * 4de4fa243SKever Yang * SPDX-License-Identifier: GPL-2.0+ 5de4fa243SKever Yang */ 6de4fa243SKever Yang 7de4fa243SKever Yang #ifndef _ASM_ARCH_CRU_RK3128_H 8de4fa243SKever Yang #define _ASM_ARCH_CRU_RK3128_H 9de4fa243SKever Yang 10de4fa243SKever Yang #include <common.h> 11de4fa243SKever Yang 12de4fa243SKever Yang #define MHz 1000000 13de4fa243SKever Yang #define OSC_HZ (24 * MHz) 14de4fa243SKever Yang 15de4fa243SKever Yang #define APLL_HZ (600 * MHz) 16de4fa243SKever Yang #define GPLL_HZ (594 * MHz) 17ba5fededSElaine Zhang #define CPLL_HZ (400 * MHz) 18efb944b6SElaine Zhang #define ACLK_BUS_HZ (148500000) 19efb944b6SElaine Zhang #define ACLK_PERI_HZ (148500000) 20de4fa243SKever Yang 21de4fa243SKever Yang /* Private data for the clock driver - used by rockchip_get_cru() */ 22de4fa243SKever Yang struct rk3128_clk_priv { 23de4fa243SKever Yang struct rk3128_cru *cru; 24efb944b6SElaine Zhang ulong gpll_hz; 2592c6b642SElaine Zhang ulong armclk_hz; 2692c6b642SElaine Zhang ulong armclk_enter_hz; 2792c6b642SElaine Zhang ulong armclk_init_hz; 2892c6b642SElaine Zhang bool sync_kernel; 2992c6b642SElaine Zhang bool set_armclk_rate; 30de4fa243SKever Yang }; 31de4fa243SKever Yang 32de4fa243SKever Yang struct rk3128_cru { 33de4fa243SKever Yang struct rk3128_pll { 34de4fa243SKever Yang unsigned int con0; 35de4fa243SKever Yang unsigned int con1; 36de4fa243SKever Yang unsigned int con2; 37de4fa243SKever Yang unsigned int con3; 38de4fa243SKever Yang } pll[4]; 39de4fa243SKever Yang unsigned int cru_mode_con; 40de4fa243SKever Yang unsigned int cru_clksel_con[35]; 41de4fa243SKever Yang unsigned int cru_clkgate_con[11]; 42de4fa243SKever Yang unsigned int reserved; 43de4fa243SKever Yang unsigned int cru_glb_srst_fst_value; 44de4fa243SKever Yang unsigned int cru_glb_srst_snd_value; 45de4fa243SKever Yang unsigned int reserved1[2]; 46de4fa243SKever Yang unsigned int cru_softrst_con[9]; 47de4fa243SKever Yang unsigned int cru_misc_con; 48de4fa243SKever Yang unsigned int reserved2[2]; 49de4fa243SKever Yang unsigned int cru_glb_cnt_th; 50de4fa243SKever Yang unsigned int reserved3[3]; 51de4fa243SKever Yang unsigned int cru_glb_rst_st; 52de4fa243SKever Yang unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1]; 53de4fa243SKever Yang unsigned int cru_sdmmc_con[2]; 54de4fa243SKever Yang unsigned int cru_sdio_con[2]; 55de4fa243SKever Yang unsigned int reserved5[2]; 56de4fa243SKever Yang unsigned int cru_emmc_con[2]; 57de4fa243SKever Yang unsigned int reserved6[4]; 58de4fa243SKever Yang unsigned int cru_pll_prg_en; 59de4fa243SKever Yang }; 60de4fa243SKever Yang check_member(rk3128_cru, cru_pll_prg_en, 0x01f0); 61de4fa243SKever Yang 62efb944b6SElaine Zhang enum rk3128_pll_id { 63efb944b6SElaine Zhang APLL, 64efb944b6SElaine Zhang DPLL, 65efb944b6SElaine Zhang CPLL, 66efb944b6SElaine Zhang GPLL, 67efb944b6SElaine Zhang PLL_COUNT, 68de4fa243SKever Yang }; 69de4fa243SKever Yang 70efb944b6SElaine Zhang struct rk3128_clk_info { 71efb944b6SElaine Zhang unsigned long id; 72efb944b6SElaine Zhang char *name; 73efb944b6SElaine Zhang bool is_cru; 74efb944b6SElaine Zhang }; 75efb944b6SElaine Zhang 76efb944b6SElaine Zhang #define RK2928_PLL_CON(x) ((x) * 0x4) 77efb944b6SElaine Zhang #define RK2928_MODE_CON 0x40 78efb944b6SElaine Zhang 79de4fa243SKever Yang enum { 80de4fa243SKever Yang /* CRU_CLK_SEL0_CON */ 81efb944b6SElaine Zhang BUS_PLL_SEL_SHIFT = 13, 82efb944b6SElaine Zhang BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT, 83efb944b6SElaine Zhang BUS_PLL_SEL_CPLL = 0, 84efb944b6SElaine Zhang BUS_PLL_SEL_GPLL, 85efb944b6SElaine Zhang BUS_PLL_SEL_GPLL_DIV2, 86efb944b6SElaine Zhang BUS_PLL_SEL_GPLL_DIV3, 87efb944b6SElaine Zhang ACLK_BUS_DIV_SHIFT = 8, 88efb944b6SElaine Zhang ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 89de4fa243SKever Yang CORE_CLK_PLL_SEL_SHIFT = 7, 90de4fa243SKever Yang CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 91de4fa243SKever Yang CORE_CLK_PLL_SEL_APLL = 0, 92de4fa243SKever Yang CORE_CLK_PLL_SEL_GPLL_DIV2, 93de4fa243SKever Yang CORE_DIV_CON_SHIFT = 0, 94de4fa243SKever Yang CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 95de4fa243SKever Yang 96de4fa243SKever Yang /* CRU_CLK_SEL1_CON */ 97efb944b6SElaine Zhang PCLK_BUS_DIV_SHIFT = 12, 98efb944b6SElaine Zhang PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT, 99efb944b6SElaine Zhang HCLK_BUS_DIV_SHIFT = 8, 100efb944b6SElaine Zhang HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT, 101de4fa243SKever Yang CORE_ACLK_DIV_SHIFT = 4, 102efb944b6SElaine Zhang CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 103efb944b6SElaine Zhang CORE_DBG_DIV_SHIFT = 0, 104efb944b6SElaine Zhang CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 105de4fa243SKever Yang 10642b2f1bcSZhaoyifeng /* CRU_CLK_SEL2_CON */ 10742b2f1bcSZhaoyifeng NANDC_PLL_SEL_SHIFT = 14, 108b10789f2SPhilipp Tomsich NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT, 10942b2f1bcSZhaoyifeng NANDC_PLL_SEL_CPLL = 0, 11042b2f1bcSZhaoyifeng NANDC_PLL_SEL_GPLL, 11142b2f1bcSZhaoyifeng NANDC_CLK_DIV_SHIFT = 8, 11242b2f1bcSZhaoyifeng NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT, 11342b2f1bcSZhaoyifeng PVTM_CLK_DIV_SHIFT = 0, 11442b2f1bcSZhaoyifeng PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT, 11542b2f1bcSZhaoyifeng 116de4fa243SKever Yang /* CRU_CLKSEL10_CON */ 117de4fa243SKever Yang PERI_PLL_SEL_SHIFT = 14, 118efb944b6SElaine Zhang PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, 119efb944b6SElaine Zhang PERI_PLL_SEL_GPLL = 0, 120efb944b6SElaine Zhang PERI_PLL_SEL_CPLL, 121efb944b6SElaine Zhang PERI_PLL_SEL_GPLL_DIV2, 122efb944b6SElaine Zhang PERI_PLL_SEL_GPLL_DIV3, 123efb944b6SElaine Zhang PCLK_PERI_DIV_SHIFT = 12, 124efb944b6SElaine Zhang PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT, 125efb944b6SElaine Zhang HCLK_PERI_DIV_SHIFT = 8, 126efb944b6SElaine Zhang HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT, 127efb944b6SElaine Zhang ACLK_PERI_DIV_SHIFT = 0, 128efb944b6SElaine Zhang ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 129de4fa243SKever Yang 130de4fa243SKever Yang /* CRU_CLKSEL11_CON */ 131a2795c33SDingqiang Lin SFC_PLL_SEL_SHIFT = 14, 132a2795c33SDingqiang Lin SFC_PLL_SEL_MASK = 3 << SFC_PLL_SEL_SHIFT, 133a2795c33SDingqiang Lin SFC_PLL_SEL_CPLL = 0, 134a2795c33SDingqiang Lin SFC_PLL_SEL_GPLL, 135a2795c33SDingqiang Lin SFC_CLK_DIV_SHIFT = 8, 136a2795c33SDingqiang Lin SFC_CLK_DIV_MASK = 0x1f << SFC_CLK_DIV_SHIFT, 137de4fa243SKever Yang MMC0_PLL_SHIFT = 6, 138de4fa243SKever Yang MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, 139de4fa243SKever Yang MMC0_SEL_APLL = 0, 140de4fa243SKever Yang MMC0_SEL_GPLL, 141de4fa243SKever Yang MMC0_SEL_GPLL_DIV2, 142de4fa243SKever Yang MMC0_SEL_24M, 143de4fa243SKever Yang MMC0_DIV_SHIFT = 0, 144de4fa243SKever Yang MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, 145de4fa243SKever Yang 146de4fa243SKever Yang /* CRU_CLKSEL12_CON */ 147de4fa243SKever Yang EMMC_PLL_SHIFT = 14, 148de4fa243SKever Yang EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 149de4fa243SKever Yang EMMC_SEL_APLL = 0, 150de4fa243SKever Yang EMMC_SEL_GPLL, 151de4fa243SKever Yang EMMC_SEL_GPLL_DIV2, 152de4fa243SKever Yang EMMC_SEL_24M, 153de4fa243SKever Yang EMMC_DIV_SHIFT = 8, 154de4fa243SKever Yang EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, 155efb944b6SElaine Zhang SDIO_PLL_SHIFT = 6, 156efb944b6SElaine Zhang SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, 157efb944b6SElaine Zhang SDIO_SEL_APLL = 0, 158efb944b6SElaine Zhang SDIO_SEL_GPLL, 159efb944b6SElaine Zhang SDIO_SEL_GPLL_DIV2, 160efb944b6SElaine Zhang SDIO_SEL_24M, 161efb944b6SElaine Zhang SDIO_DIV_SHIFT = 0, 162efb944b6SElaine Zhang SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, 163de4fa243SKever Yang 164eb4fc8a1SDavid Wu /* CLKSEL_CON24 */ 165eb4fc8a1SDavid Wu SARADC_DIV_CON_SHIFT = 8, 166eb4fc8a1SDavid Wu SARADC_DIV_CON_MASK = GENMASK(15, 8), 167eb4fc8a1SDavid Wu SARADC_DIV_CON_WIDTH = 8, 168582fa222SElaine Zhang CLK_CRYPTO_DIV_CON_SHIFT= 0, 169582fa222SElaine Zhang CLK_CRYPTO_DIV_CON_MASK = GENMASK(1, 0), 170eb4fc8a1SDavid Wu 171*7f619f26SElaine Zhang /* CLKSEL_CON25 */ 172*7f619f26SElaine Zhang SPI_PLL_SEL_SHIFT = 8, 173*7f619f26SElaine Zhang SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT, 174*7f619f26SElaine Zhang SPI_PLL_SEL_CPLL = 0, 175*7f619f26SElaine Zhang SPI_PLL_SEL_GPLL, 176*7f619f26SElaine Zhang SPI_PLL_SEL_GPLL_DIV2, 177*7f619f26SElaine Zhang SPI_DIV_SHIFT = 0, 178*7f619f26SElaine Zhang SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT, 179*7f619f26SElaine Zhang 1803e3a3170SElaine Zhang /* CRU_CLKSEL27_CON*/ 1813e3a3170SElaine Zhang DCLK_VOP_SEL_SHIFT = 0, 1823e3a3170SElaine Zhang DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, 1833e3a3170SElaine Zhang DCLK_VOP_PLL_SEL_CPLL = 0, 1843e3a3170SElaine Zhang DCLK_VOP_DIV_CON_SHIFT = 8, 18543ae10fdSPhilipp Tomsich DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, 1863e3a3170SElaine Zhang 1873e3a3170SElaine Zhang /* CRU_CLKSEL31_CON */ 1883e3a3170SElaine Zhang VIO0_PLL_SHIFT = 5, 1893e3a3170SElaine Zhang VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT, 1903e3a3170SElaine Zhang VI00_SEL_CPLL = 0, 1913e3a3170SElaine Zhang VIO0_SEL_GPLL, 1923e3a3170SElaine Zhang VIO0_DIV_SHIFT = 0, 1933e3a3170SElaine Zhang VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT, 1943e3a3170SElaine Zhang VIO1_PLL_SHIFT = 13, 1953e3a3170SElaine Zhang VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT, 1963e3a3170SElaine Zhang VI01_SEL_CPLL = 0, 1973e3a3170SElaine Zhang VIO1_SEL_GPLL, 1983e3a3170SElaine Zhang VIO1_DIV_SHIFT = 8, 1993e3a3170SElaine Zhang VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT, 2003e3a3170SElaine Zhang 201de4fa243SKever Yang /* CRU_SOFTRST5_CON */ 202de4fa243SKever Yang DDRCTRL_PSRST_SHIFT = 11, 203de4fa243SKever Yang DDRCTRL_SRST_SHIFT = 10, 204de4fa243SKever Yang DDRPHY_PSRST_SHIFT = 9, 205de4fa243SKever Yang DDRPHY_SRST_SHIFT = 8, 206de4fa243SKever Yang }; 207de4fa243SKever Yang #endif 208