| #
7f619f26 |
| 09-Jun-2020 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3128: add support to set and get spi clock
Change-Id: I4ac874ba0542474baf18491f986f401c831a5ad4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
582fa222 |
| 16-May-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3128: support crypto clk get/set rate
Change-Id: I3a7d71a481aca04c9e6c0547cfc05a8106f79423
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
92c6b642 |
| 23-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3128: print arm enter and init rate
Change-Id: I0be1752522a83a2d111870e5a8ac95f92bd7f9a5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
a2795c33 |
| 07-Nov-2018 |
Dingqiang Lin <jon.lin@rock-chips.com> |
clk: rockchip: rk312x: add sfc clk init
Change-Id: I5edf0a4b650a57a48f837fa3e007cfaf6a733f92
Signed-off-by: Dingqiang Lin <jon.lin@rock-chips.com>
|
| #
ba5feded |
| 28-Sep-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk312x: add cpll freq init
Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop displ
clk: rockchip: rk312x: add cpll freq init
Add cpll freq setting in rkclk_init.
If have vop display, the cpll is just for dclk vop.
The cpll freq will be setting by dclk freq set.
But if no vop display, the cpll need to set init freq for other
children clk.
Change-Id: Ia45892dd3c8efb77cf32b631329d927aceb8dd86
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
efb944b6 |
| 26-Jul-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk3128: support more clks to set and get rate
Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.
Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e
rockchip: clk: rk3128: support more clks to set and get rate
Make clock ids consistent with kernel.
support more clks to set and get rate.
add clk init.
Change-Id: I1e6b5734887e0bd5d845f1286f10eb0e3e42bc08
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
43ae10fd |
| 01-Dec-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.
Fixes
UPSTREAM: rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Change-Id: I6132623ce069ec6c6cd59a01580e795142864862
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 4fc495e9e2e497afee383294a6ee9212e9a8bd73)
show more ...
|
| #
b10789f2 |
| 01-Dec-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
UPSTREAM: rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK
The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.
Fixes: 9246d9e ("rockchip: rk3128: add c
UPSTREAM: rockchip: clk: rk3128: fix NANDC_PLL_SEL_MASK
The PLL selector field for NANDC is only 2 bits wide.
This fixes an 'int-overflow on shift' warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Change-Id: I4d6d7c51633eb7cd0fbfb1c6b7c501cf8c0fcf81
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit cd401abcd532c59cdaaf6ffeed762386c1813e58)
show more ...
|
| #
3e3a3170 |
| 20-Oct-2017 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk3128: support dclk_lcdc and aclk_vio setting
support vop clk setting freq, for uboot logo display.
Change-Id: I766bdc2c3a13d0ee92f81fbd7a30b7cc87c2dceb
Signed-off-by: Elaine Zhang
clk: rockchip: rk3128: support dclk_lcdc and aclk_vio setting
support vop clk setting freq, for uboot logo display.
Change-Id: I766bdc2c3a13d0ee92f81fbd7a30b7cc87c2dceb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|
| #
42b2f1bc |
| 18-Oct-2017 |
Zhaoyifeng <zyf@rock-chips.com> |
3128: clock: config nand controller working clock max 150Mhz
nandc working clock div from gpll and max clock config 150Mhz
while gpll config as 600Mhz.
Change-Id: I893d453d031a0ddd0cd79111699d36000
3128: clock: config nand controller working clock max 150Mhz
nandc working clock div from gpll and max clock config 150Mhz
while gpll config as 600Mhz.
Change-Id: I893d453d031a0ddd0cd79111699d3600095c6e4f
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
show more ...
|
| #
eb4fc8a1 |
| 16-Oct-2017 |
David Wu <david.wu@rock-chips.com> |
clk: rockchip: Add rk3128 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: I973
clk: rockchip: Add rk3128 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: I973b5f50b81559f054ca552ab69ec176cbe3abaa
Signed-off-by: David Wu <david.wu@rock-chips.com>
show more ...
|
| #
de4fa243 |
| 10-Mar-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3128: add clock driver
Add rk3128 clock driver and cru structure definition.
Change-Id: Ib6e17f56b2e7e6cc6cdf06f8d9ac44c062b5b6e3
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|