clk: rockchip: rk3368: support crypto clk get/set rate

Change-Id: I736fdda1d994ebdb59c68f8be209bae0e206be99
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3368: support pclk_wdt get rate

Change-Id: I8253532cfa6a1d492d68b0e778f625621cad5dab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

clk: rockchip: rk3368: print arm enter and init rate

Change-Id: Ib201cf442ce7398bbe8009ce9b7de9dc1f53c587
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb49

rockchip: clk: rk3368: support more clks to set and get rate

Make clock ids consistent with kernel.
Support more clks to set and get rate.
Add clk dump.

Change-Id: I348c98ce81ce76af9c492a30480fcb495da7ed79
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb

clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb7
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

show more ...

rockchip: clk: Add rk3368 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I47c

rockchip: clk: Add rk3368 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I47cc95d7e2cbf026bc34042cef4c2fe636bae674
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 615514c16dee4d43bd584ea326a5a56ebcb89c85)

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-rockchip

rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementa

rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
- rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

rockchip: clk: rk3368: implement MMC/SD clock reparenting

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving t

rockchip: clk: rk3368: implement MMC/SD clock reparenting

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
* always generate a clock less-than-or-equal to the requested clock
* support reparenting among the CPLL, GPLL and OSC24M parents to
generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
- rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM. To

rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM. To
do so, we need to reset the two DMA engines, which in turn requires
the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
appropriate bits in the CRU.

As the ATF correctly initialises security (and only leaves EL3 after
doing so), this can not pose a security issue.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv

The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always

rockchip: clk: rk3368: remove unused fields from rk3368_clk_priv

The rk3368_clk_priv has two unused fields: rate, has_bwadj. This
removes them as there's no need for either (i.e. has_bwadj is always
true for the RK3368, according to its TRM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixe

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

show more ...

rockchip: rk3368: Add clock driver

Add driver to setup the various PLLs and peripheral
clocks on the RK3368.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium

rockchip: rk3368: Add clock driver

Add driver to setup the various PLLs and peripheral
clocks on the RK3368.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...