145a3782aSElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 245a3782aSElaine Zhang /* 345a3782aSElaine Zhang * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 445a3782aSElaine Zhang */ 545a3782aSElaine Zhang 645a3782aSElaine Zhang #ifndef _ASM_ARCH_CRU_rk1808_H 745a3782aSElaine Zhang #define _ASM_ARCH_CRU_rk1808_H 845a3782aSElaine Zhang 945a3782aSElaine Zhang #include <common.h> 1045a3782aSElaine Zhang 1145a3782aSElaine Zhang #define MHz 1000000 1245a3782aSElaine Zhang #define KHz 1000 1345a3782aSElaine Zhang #define OSC_HZ (24 * MHz) 1408b717abSLin Huang #define APLL_HZ (1200 * MHz) 15dad14895SElaine Zhang #define PCLK_PMU_HZ (100 * MHz) 16*28e9e98aSJason Zhu #define GPLL_HZ (594 * MHz) 1745a3782aSElaine Zhang 1845a3782aSElaine Zhang /* PX30 pll id */ 1945a3782aSElaine Zhang enum rk1808_pll_id { 2045a3782aSElaine Zhang APLL, 2145a3782aSElaine Zhang DPLL, 2245a3782aSElaine Zhang CPLL, 2345a3782aSElaine Zhang GPLL, 2445a3782aSElaine Zhang NPLL, 2545a3782aSElaine Zhang PPLL, 2645a3782aSElaine Zhang PLL_COUNT, 2745a3782aSElaine Zhang }; 2845a3782aSElaine Zhang 2945a3782aSElaine Zhang struct rk1808_clk_info { 3045a3782aSElaine Zhang unsigned long id; 3145a3782aSElaine Zhang char *name; 3245a3782aSElaine Zhang bool is_cru; 3345a3782aSElaine Zhang }; 3445a3782aSElaine Zhang 3545a3782aSElaine Zhang /* Private data for the clock driver - used by rockchip_get_cru() */ 3645a3782aSElaine Zhang struct rk1808_clk_priv { 3745a3782aSElaine Zhang struct rk1808_cru *cru; 3845a3782aSElaine Zhang ulong armclk_hz; 3945a3782aSElaine Zhang ulong cpll_hz; 4045a3782aSElaine Zhang ulong gpll_hz; 4145a3782aSElaine Zhang ulong npll_hz; 42ed6f5d94SElaine Zhang ulong armclk_enter_hz; 43ed6f5d94SElaine Zhang ulong armclk_init_hz; 44ed6f5d94SElaine Zhang bool sync_kernel; 45ed6f5d94SElaine Zhang bool set_armclk_rate; 4645a3782aSElaine Zhang }; 4745a3782aSElaine Zhang 4845a3782aSElaine Zhang struct rk1808_pll { 4945a3782aSElaine Zhang unsigned int con0; 5045a3782aSElaine Zhang unsigned int con1; 5145a3782aSElaine Zhang unsigned int con2; 5245a3782aSElaine Zhang unsigned int con3; 5345a3782aSElaine Zhang unsigned int con4; 5445a3782aSElaine Zhang unsigned int reserved0[3]; 5545a3782aSElaine Zhang }; 5645a3782aSElaine Zhang 5745a3782aSElaine Zhang struct rk1808_cru { 5845a3782aSElaine Zhang struct rk1808_pll pll[5]; 5945a3782aSElaine Zhang unsigned int mode; 6045a3782aSElaine Zhang unsigned int misc; 6145a3782aSElaine Zhang unsigned int misc1; 6245a3782aSElaine Zhang unsigned int reserved2[1]; 6345a3782aSElaine Zhang unsigned int glb_cnt_th; 6445a3782aSElaine Zhang unsigned int glb_rst_st; 6545a3782aSElaine Zhang unsigned int glb_srst_fst; 6645a3782aSElaine Zhang unsigned int glb_srst_snd; 6745a3782aSElaine Zhang unsigned int glb_rst_con; 6845a3782aSElaine Zhang unsigned int reserved3[7]; 6945a3782aSElaine Zhang unsigned int hwffc_con0; 7045a3782aSElaine Zhang unsigned int reserved4; 7145a3782aSElaine Zhang unsigned int hwffc_th; 7245a3782aSElaine Zhang unsigned int hwffc_intst; 7345a3782aSElaine Zhang unsigned int apll_con0_s; 7445a3782aSElaine Zhang unsigned int apll_con1_s; 7545a3782aSElaine Zhang unsigned int clksel_con0_s; 7645a3782aSElaine Zhang unsigned int reserved5; 7745a3782aSElaine Zhang unsigned int clksel_con[73]; 7845a3782aSElaine Zhang unsigned int reserved6[3]; 7945a3782aSElaine Zhang unsigned int clkgate_con[20]; 8045a3782aSElaine Zhang unsigned int ssgtbl[32]; 8145a3782aSElaine Zhang unsigned int softrst_con[16]; 8245a3782aSElaine Zhang unsigned int reserved7[(0x380 - 0x33c) / 4 - 1]; 8345a3782aSElaine Zhang unsigned int sdmmc_con[2]; 8445a3782aSElaine Zhang unsigned int sdio_con[2]; 8545a3782aSElaine Zhang unsigned int emmc_con[2]; 8645a3782aSElaine Zhang unsigned int reserved8[(0x400 - 0x394) / 4 - 1]; 8745a3782aSElaine Zhang unsigned int autocs_con[10]; 8845a3782aSElaine Zhang unsigned int reserved9[(0x4000 - 0x424) / 4 - 1]; 8945a3782aSElaine Zhang struct rk1808_pll pmu_pll; 9045a3782aSElaine Zhang unsigned int pmu_mode; 9145a3782aSElaine Zhang unsigned int reserved10[(0x4040 - 0x4020) / 4 - 1]; 9245a3782aSElaine Zhang unsigned int pmu_clksel_con[8]; 9345a3782aSElaine Zhang unsigned int reserved11[(0x4080 - 0x405c) / 4 - 1]; 9445a3782aSElaine Zhang unsigned int pmu_clkgate_con[2]; 9545a3782aSElaine Zhang unsigned int reserved12[(0x40c0 - 0x4084) / 4 - 1]; 9645a3782aSElaine Zhang unsigned int pmu_autocs_con[2]; 9745a3782aSElaine Zhang }; 9845a3782aSElaine Zhang 9945a3782aSElaine Zhang check_member(rk1808_cru, pmu_autocs_con[0], 0x40c0); 10045a3782aSElaine Zhang 10145a3782aSElaine Zhang #define RK1808_PLL_CON(x) ((x) * 0x4) 10245a3782aSElaine Zhang #define RK1808_MODE_CON 0xa0 10345a3782aSElaine Zhang #define RK1808_PMU_PLL_CON(x) ((x) * 0x4 + 0x4000) 10445a3782aSElaine Zhang #define RK1808_PMU_MODE_CON 0x4020 10545a3782aSElaine Zhang 10645a3782aSElaine Zhang enum { 10745a3782aSElaine Zhang /* CRU_CLK_SEL0_CON */ 10845a3782aSElaine Zhang CORE_ACLK_DIV_SHIFT = 12, 10945a3782aSElaine Zhang CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 11045a3782aSElaine Zhang CORE_DBG_DIV_SHIFT = 8, 11145a3782aSElaine Zhang CORE_DBG_DIV_MASK = 0x03 << CORE_DBG_DIV_SHIFT, 11245a3782aSElaine Zhang CORE_CLK_PLL_SEL_SHIFT = 7, 11345a3782aSElaine Zhang CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, 11445a3782aSElaine Zhang CORE_CLK_PLL_SEL_APLL = 0, 11545a3782aSElaine Zhang CORE_CLK_PLL_SEL_GPLL, 11645a3782aSElaine Zhang CORE_DIV_CON_SHIFT = 0, 11745a3782aSElaine Zhang CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT, 11845a3782aSElaine Zhang 11945a3782aSElaine Zhang /* CRU_CLK_SEL4_CON */ 12045a3782aSElaine Zhang ACLK_VOP_PLL_SEL_GPLL = 0, 12145a3782aSElaine Zhang ACLK_VOP_PLL_SEL_CPLL = 1, 12245a3782aSElaine Zhang ACLK_VOP_PLL_SEL_SHIFT = 7, 12345a3782aSElaine Zhang ACLK_VOP_PLL_SEL_MASK = 1 << ACLK_VOP_PLL_SEL_SHIFT, 12445a3782aSElaine Zhang ACLK_VOP_DIV_CON_SHIFT = 0, 12545a3782aSElaine Zhang ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 12645a3782aSElaine Zhang HCLK_VOP_DIV_CON_SHIFT = 8, 12745a3782aSElaine Zhang HCLK_VOP_DIV_CON_MASK = 0x1f << HCLK_VOP_DIV_CON_SHIFT, 12845a3782aSElaine Zhang 12945a3782aSElaine Zhang /* CRU_CLK_SEL5_CON */ 1301ae6d6e5SElaine Zhang DCLK_VOPRAW_SEL_VOPRAW = 0, 1311ae6d6e5SElaine Zhang DCLK_VOPRAW_SEL_VOPRAW_FRAC = 1, 1321ae6d6e5SElaine Zhang DCLK_VOPRAW_SEL_XIN24M = 2, 13345a3782aSElaine Zhang DCLK_VOPRAW_SEL_SHIFT = 14, 13445a3782aSElaine Zhang DCLK_VOPRAW_SEL_MASK = 3 << DCLK_VOPRAW_SEL_SHIFT, 13545a3782aSElaine Zhang DCLK_VOPRAW_PLL_SEL_CPLL = 0, 13645a3782aSElaine Zhang DCLK_VOPRAW_PLL_SEL_GPLL = 1, 13745a3782aSElaine Zhang DCLK_VOPRAW_PLL_SEL_NPLL = 2, 13845a3782aSElaine Zhang DCLK_VOPRAW_PLL_SEL_SHIFT = 10, 13945a3782aSElaine Zhang DCLK_VOPRAW_PLL_SEL_MASK = 3 << DCLK_VOPRAW_PLL_SEL_SHIFT, 14045a3782aSElaine Zhang DCLK_VOPRAW_DIV_CON_SHIFT = 0, 1411ae6d6e5SElaine Zhang DCLK_VOPRAW_DIV_CON_MASK = 0xff << DCLK_VOPRAW_DIV_CON_SHIFT, 14245a3782aSElaine Zhang 14345a3782aSElaine Zhang /* CRU_CLK_SEL7_CON */ 1441ae6d6e5SElaine Zhang DCLK_VOPLITE_SEL_VOPRAW = 0, 1451ae6d6e5SElaine Zhang DCLK_VOPLITE_SEL_VOPRAW_FRAC = 1, 1461ae6d6e5SElaine Zhang DCLK_VOPLITE_SEL_XIN24M = 2, 14745a3782aSElaine Zhang DCLK_VOPLITE_SEL_SHIFT = 14, 14845a3782aSElaine Zhang DCLK_VOPLITE_SEL_MASK = 3 << DCLK_VOPLITE_SEL_SHIFT, 14945a3782aSElaine Zhang DCLK_VOPLITE_PLL_SEL_CPLL = 0, 15045a3782aSElaine Zhang DCLK_VOPLITE_PLL_SEL_GPLL = 1, 15145a3782aSElaine Zhang DCLK_VOPLITE_PLL_SEL_NPLL = 2, 15245a3782aSElaine Zhang DCLK_VOPLITE_PLL_SEL_SHIFT = 10, 15345a3782aSElaine Zhang DCLK_VOPLITE_PLL_SEL_MASK = 3 << DCLK_VOPLITE_PLL_SEL_SHIFT, 15445a3782aSElaine Zhang DCLK_VOPLITE_DIV_CON_SHIFT = 0, 1551ae6d6e5SElaine Zhang DCLK_VOPLITE_DIV_CON_MASK = 0xff << DCLK_VOPLITE_DIV_CON_SHIFT, 15645a3782aSElaine Zhang 15745a3782aSElaine Zhang /* CRU_CLK_SEL19_CON */ 15845a3782aSElaine Zhang CLK_PERI_PLL_SEL_GPLL = 0, 15945a3782aSElaine Zhang CLK_PERI_PLL_SEL_CPLL = 1, 16045a3782aSElaine Zhang CLK_PERI_PLL_SEL_SHIFT = 15, 16145a3782aSElaine Zhang CLK_PERI_PLL_SEL_MASK = 1 << CLK_PERI_PLL_SEL_SHIFT, 16245a3782aSElaine Zhang LSCLK_PERI_DIV_CON_SHIFT = 8, 16345a3782aSElaine Zhang LSCLK_PERI_DIV_CON_MASK = 0x1f << LSCLK_PERI_DIV_CON_SHIFT, 16445a3782aSElaine Zhang MSCLK_PERI_DIV_CON_SHIFT = 0, 16545a3782aSElaine Zhang MSCLK_PERI_DIV_CON_MASK = 0x1f << MSCLK_PERI_DIV_CON_SHIFT, 16645a3782aSElaine Zhang 16745a3782aSElaine Zhang /* CRU_CLKSEL24_CON */ 16845a3782aSElaine Zhang EMMC_PLL_SHIFT = 14, 16945a3782aSElaine Zhang EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, 17045a3782aSElaine Zhang EMMC_SEL_GPLL = 0, 17145a3782aSElaine Zhang EMMC_SEL_CPLL, 17245a3782aSElaine Zhang EMMC_SEL_NPLL, 17345a3782aSElaine Zhang EMMC_SEL_24M, 17445a3782aSElaine Zhang EMMC_DIV_SHIFT = 0, 17545a3782aSElaine Zhang EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT, 17645a3782aSElaine Zhang 17745a3782aSElaine Zhang /* CRU_CLKSEL25_CON */ 17845a3782aSElaine Zhang EMMC_CLK_SEL_SHIFT = 15, 17945a3782aSElaine Zhang EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT, 18045a3782aSElaine Zhang EMMC_CLK_SEL_EMMC = 0, 18145a3782aSElaine Zhang EMMC_CLK_SEL_EMMC_DIV50, 18245a3782aSElaine Zhang EMMC_DIV50_SHIFT = 0, 18345a3782aSElaine Zhang EMMC_DIV50_MASK = 0xff << EMMC_DIV_SHIFT, 18445a3782aSElaine Zhang 185b9f59722SElaine Zhang /* CRU_CLKSEL26_CON */ 186b9f59722SElaine Zhang GMAC_PLL_SEL_SHIFT = 14, 187b9f59722SElaine Zhang GMAC_PLL_SEL_MASK = 3 << GMAC_PLL_SEL_SHIFT, 188b9f59722SElaine Zhang GMAC_PLL_SEL_CPLL = 0, 189b9f59722SElaine Zhang GMAC_PLL_SEL_NPLL, 190b9f59722SElaine Zhang GMAC_PLL_SEL_PPLL, 191b9f59722SElaine Zhang CLK_GMAC_DIV_SHIFT = 8, 192b9f59722SElaine Zhang CLK_GMAC_DIV_MASK = 0x1f << CLK_GMAC_DIV_SHIFT, 193b9f59722SElaine Zhang SFC_PLL_SEL_SHIFT = 7, 194b9f59722SElaine Zhang SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, 195b9f59722SElaine Zhang SFC_DIV_CON_SHIFT = 0, 196b9f59722SElaine Zhang SFC_DIV_CON_MASK = 0x7f, 197b9f59722SElaine Zhang 19845a3782aSElaine Zhang /* CRU_CLK_SEL27_CON */ 19945a3782aSElaine Zhang CLK_BUS_PLL_SEL_GPLL = 0, 20045a3782aSElaine Zhang CLK_BUS_PLL_SEL_CPLL = 1, 20145a3782aSElaine Zhang CLK_BUS_PLL_SEL_SHIFT = 15, 20245a3782aSElaine Zhang CLK_BUS_PLL_SEL_MASK = 1 << CLK_BUS_PLL_SEL_SHIFT, 20345a3782aSElaine Zhang HSCLK_BUS_DIV_CON_SHIFT = 8, 20445a3782aSElaine Zhang HSCLK_BUS_DIV_CON_MASK = 0x1f << HSCLK_BUS_DIV_CON_SHIFT, 205b9f59722SElaine Zhang RGMII_CLK_SEL_SHIFT = 2, 206b9f59722SElaine Zhang RGMII_CLK_SEL_MASK = 3 << RGMII_CLK_SEL_SHIFT, 207b9f59722SElaine Zhang RGMII_CLK_SEL_125M = 0, 208b9f59722SElaine Zhang RGMII_CLK_SEL_2M = 2, 209b9f59722SElaine Zhang RGMIIC_CLK_SEL_25M = 3, 210b9f59722SElaine Zhang RMII_CLK_SEL_SHIFT = 1, 211b9f59722SElaine Zhang RMII_CLK_SEL_MASK = 1 << RMII_CLK_SEL_SHIFT, 212b9f59722SElaine Zhang RMII_EXTCLK_SEL_SHIFT = 0, 213b9f59722SElaine Zhang RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, 214b9f59722SElaine Zhang RMII_EXTCLK_SEL_INT = 0, 215b9f59722SElaine Zhang RMII_EXTCLK_SEL_EXT, 21645a3782aSElaine Zhang 21745a3782aSElaine Zhang /* CRU_CLK_SEL28_CON */ 21845a3782aSElaine Zhang MSCLK_BUS_DIV_CON_SHIFT = 8, 21945a3782aSElaine Zhang MSCLK_BUS_DIV_CON_MASK = 0x1f << MSCLK_BUS_DIV_CON_SHIFT, 22045a3782aSElaine Zhang LSCLK_BUS_DIV_CON_SHIFT = 0, 22145a3782aSElaine Zhang LSCLK_BUS_DIV_CON_MASK = 0x1f << LSCLK_BUS_DIV_CON_SHIFT, 22245a3782aSElaine Zhang 22332f0452dSElaine Zhang /* CRU_CLK_SEL29_CON */ 22432f0452dSElaine Zhang CRYPTO_APK_SEL_SHIFT = 15, 22532f0452dSElaine Zhang CRYPTO_APK_PLL_SEL_MASK = 1 << CRYPTO_APK_SEL_SHIFT, 22632f0452dSElaine Zhang CRYPTO_PLL_SEL_GPLL = 0, 22732f0452dSElaine Zhang CRYPTO_PLL_SEL_CPLL, 22832f0452dSElaine Zhang CRYPTO_APK_DIV_SHIFT = 8, 22932f0452dSElaine Zhang CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT, 23032f0452dSElaine Zhang CRYPTO_PLL_SEL_SHIFT = 7, 23132f0452dSElaine Zhang CRYPTO_PLL_SEL_MASK = 1 << CRYPTO_PLL_SEL_SHIFT, 23232f0452dSElaine Zhang CRYPTO_DIV_SHIFT = 0, 23332f0452dSElaine Zhang CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT, 23432f0452dSElaine Zhang 23545a3782aSElaine Zhang /* CRU_CLK_SEL59_CON */ 23645a3782aSElaine Zhang CLK_I2C_PLL_SEL_GPLL = 0, 23745a3782aSElaine Zhang CLK_I2C_PLL_SEL_24M, 23845a3782aSElaine Zhang CLK_I2C2_PLL_SEL_SHIFT = 15, 23945a3782aSElaine Zhang CLK_I2C2_DIV_CON_SHIFT = 8, 24045a3782aSElaine Zhang CLK_I2C2_DIV_CON_MASK = 0x7f << CLK_I2C2_DIV_CON_SHIFT, 24145a3782aSElaine Zhang CLK_I2C2_PLL_SEL_MASK = 1 << CLK_I2C2_PLL_SEL_SHIFT, 24245a3782aSElaine Zhang CLK_I2C1_PLL_SEL_SHIFT = 7, 24345a3782aSElaine Zhang CLK_I2C1_DIV_CON_SHIFT = 0, 24445a3782aSElaine Zhang CLK_I2C1_DIV_CON_MASK = 0x7f, 24545a3782aSElaine Zhang CLK_I2C1_PLL_SEL_MASK = 1 << CLK_I2C1_PLL_SEL_SHIFT, 24645a3782aSElaine Zhang 24745a3782aSElaine Zhang /* CRU_CLK_SEL60_CON */ 24845a3782aSElaine Zhang CLK_SPI_PLL_SEL_GPLL = 0, 24945a3782aSElaine Zhang CLK_SPI_PLL_SEL_24M, 25045a3782aSElaine Zhang CLK_SPI0_PLL_SEL_SHIFT = 15, 25145a3782aSElaine Zhang CLK_SPI0_DIV_CON_SHIFT = 8, 25245a3782aSElaine Zhang CLK_SPI0_DIV_CON_MASK = 0x7f << CLK_SPI0_DIV_CON_SHIFT, 25345a3782aSElaine Zhang CLK_SPI0_PLL_SEL_MASK = 1 << CLK_SPI0_PLL_SEL_SHIFT, 25445a3782aSElaine Zhang CLK_I2C3_PLL_SEL_SHIFT = 7, 25545a3782aSElaine Zhang CLK_I2C3_DIV_CON_SHIFT = 0, 25645a3782aSElaine Zhang CLK_I2C3_DIV_CON_MASK = 0x7f, 25745a3782aSElaine Zhang CLK_I2C3_PLL_SEL_MASK = 1 << CLK_I2C3_PLL_SEL_SHIFT, 25845a3782aSElaine Zhang 25945a3782aSElaine Zhang /* CRU_CLK_SEL61_CON */ 26045a3782aSElaine Zhang CLK_SPI2_PLL_SEL_SHIFT = 15, 26145a3782aSElaine Zhang CLK_SPI2_DIV_CON_SHIFT = 8, 26245a3782aSElaine Zhang CLK_SPI2_DIV_CON_MASK = 0x7f << CLK_SPI2_DIV_CON_SHIFT, 26345a3782aSElaine Zhang CLK_SPI2_PLL_SEL_MASK = 1 << CLK_SPI2_PLL_SEL_SHIFT, 26445a3782aSElaine Zhang CLK_SPI1_PLL_SEL_SHIFT = 7, 26545a3782aSElaine Zhang CLK_SPI1_DIV_CON_SHIFT = 0, 26645a3782aSElaine Zhang CLK_SPI1_DIV_CON_MASK = 0x7f, 26745a3782aSElaine Zhang CLK_SPI1_PLL_SEL_MASK = 1 << CLK_SPI1_PLL_SEL_SHIFT, 26845a3782aSElaine Zhang 26945a3782aSElaine Zhang /* CRU_CLK_SEL62_CON */ 27045a3782aSElaine Zhang CLK_TSADC_DIV_CON_SHIFT = 0, 27145a3782aSElaine Zhang CLK_TSADC_DIV_CON_MASK = 0x3ff, 27245a3782aSElaine Zhang 27345a3782aSElaine Zhang /* CRU_CLK_SEL63_CON */ 27445a3782aSElaine Zhang CLK_SARADC_DIV_CON_SHIFT = 0, 27545a3782aSElaine Zhang CLK_SARADC_DIV_CON_MASK = 0x3ff, 27645a3782aSElaine Zhang 27745a3782aSElaine Zhang /* CRU_CLK_SEL69_CON */ 27845a3782aSElaine Zhang CLK_PWM_PLL_SEL_GPLL = 0, 27945a3782aSElaine Zhang CLK_PWM_PLL_SEL_24M, 28045a3782aSElaine Zhang CLK_PWM1_PLL_SEL_SHIFT = 15, 28145a3782aSElaine Zhang CLK_PWM1_DIV_CON_SHIFT = 8, 28245a3782aSElaine Zhang CLK_PWM1_DIV_CON_MASK = 0x7f << CLK_PWM1_DIV_CON_SHIFT, 28345a3782aSElaine Zhang CLK_PWM1_PLL_SEL_MASK = 1 << CLK_PWM1_PLL_SEL_SHIFT, 28445a3782aSElaine Zhang CLK_PWM0_PLL_SEL_SHIFT = 7, 28545a3782aSElaine Zhang CLK_PWM0_DIV_CON_SHIFT = 0, 28645a3782aSElaine Zhang CLK_PWM0_DIV_CON_MASK = 0x7f, 28745a3782aSElaine Zhang CLK_PWM0_PLL_SEL_MASK = 1 << CLK_PWM0_PLL_SEL_SHIFT, 28845a3782aSElaine Zhang 28945a3782aSElaine Zhang /* CRU_CLK_SEL70_CON */ 29045a3782aSElaine Zhang CLK_PWM2_PLL_SEL_SHIFT = 7, 29145a3782aSElaine Zhang CLK_PWM2_DIV_CON_SHIFT = 0, 29245a3782aSElaine Zhang CLK_PWM2_DIV_CON_MASK = 0x7f, 29345a3782aSElaine Zhang CLK_PWM2_PLL_SEL_MASK = 1 << CLK_PWM2_PLL_SEL_SHIFT, 29445a3782aSElaine Zhang 29545a3782aSElaine Zhang /* CRU_CLK_SEL71_CON */ 29645a3782aSElaine Zhang CLK_I2C5_PLL_SEL_SHIFT = 15, 29745a3782aSElaine Zhang CLK_I2C5_DIV_CON_SHIFT = 8, 29845a3782aSElaine Zhang CLK_I2C5_DIV_CON_MASK = 0x7f << CLK_I2C5_DIV_CON_SHIFT, 29945a3782aSElaine Zhang CLK_I2C5_PLL_SEL_MASK = 1 << CLK_I2C5_PLL_SEL_SHIFT, 30045a3782aSElaine Zhang CLK_I2C4_PLL_SEL_SHIFT = 7, 30145a3782aSElaine Zhang CLK_I2C4_DIV_CON_SHIFT = 0, 30245a3782aSElaine Zhang CLK_I2C4_DIV_CON_MASK = 0x7f, 30345a3782aSElaine Zhang CLK_I2C4_PLL_SEL_MASK = 1 << CLK_I2C4_PLL_SEL_SHIFT, 30445a3782aSElaine Zhang 30545a3782aSElaine Zhang /* CRU_PMU_CLK_SEL7_CON */ 30645a3782aSElaine Zhang CLK_I2C0_PLL_SEL_PPLL = 0, 30745a3782aSElaine Zhang CLK_I2C0_PLL_SEL_SHIFT = 15, 30845a3782aSElaine Zhang CLK_I2C0_DIV_CON_SHIFT = 8, 30945a3782aSElaine Zhang CLK_I2C0_PLL_SEL_MASK = 1 << CLK_I2C0_PLL_SEL_SHIFT, 31045a3782aSElaine Zhang CLK_I2C0_DIV_CON_MASK = 0x3f << CLK_I2C0_DIV_CON_SHIFT, 311dad14895SElaine Zhang 312dad14895SElaine Zhang /* PMUCRU_CLK_SEL0_CON */ 313dad14895SElaine Zhang PCLK_PMU_DIV_CON_SHIFT = 0, 314dad14895SElaine Zhang PCLK_PMU_DIV_CON_MASK = 0x1f << PCLK_PMU_DIV_CON_SHIFT, 31545a3782aSElaine Zhang }; 31645a3782aSElaine Zhang #endif 317