| #
76534374 |
| 15-Jun-2022 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
clk: rockchip: rv1106: change APLL_HZ to 1.1G
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: Ia017309069dd9ff0d3ca6e1dd0d66217a27e09fb
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| #
b81ef8b2 |
| 15-Apr-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add dclk_decom
Change-Id: Ied47331ddb33fc73491875743667f1e4afcb8eb2
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
32914815 |
| 26-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add grf clk
add grf clk for emmc\sdio\sdmmc sample and drv.
Change-Id: I35c1c7aa0387e3d62fed37264a23a230e45e7194
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
75bf999a |
| 22-Mar-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rv1106: add core div setting
fix kernel clk summary:
pll_apll 1 1 0 816000000
apll 1 1 0 816
clk: rockchip: rv1106: add core div setting
fix kernel clk summary:
pll_apll 1 1 0 816000000
apll 1 1 0 816000000
armclk 1 1 0 408000000
Change-Id: I4fc0a20d36c6768b4dd26f61ef74c28d2b0c97ff
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
a5a5ddb9 |
| 18-Jan-2022 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b
Signed-off-by: Elaine Zhang <zhangqing@
clk: rockchip: Add clock controller for the RV1106
Add the clock tree definition for the new RV1106 SoC.
Change-Id: Ifc9778851608337fda121297cc0d1200706cf72b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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