1a5a5ddb9SElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 2a5a5ddb9SElaine Zhang /* 3a5a5ddb9SElaine Zhang * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4a5a5ddb9SElaine Zhang * Author: Elaine Zhang <zhangqing@rock-chips.com> 5a5a5ddb9SElaine Zhang */ 6a5a5ddb9SElaine Zhang 7a5a5ddb9SElaine Zhang #ifndef _ASM_ARCH_CRU_RV1106_H 8a5a5ddb9SElaine Zhang #define _ASM_ARCH_CRU_RV1106_H 9a5a5ddb9SElaine Zhang 10a5a5ddb9SElaine Zhang #include <common.h> 11a5a5ddb9SElaine Zhang 12a5a5ddb9SElaine Zhang #define MHz 1000000 13a5a5ddb9SElaine Zhang #define KHz 1000 14a5a5ddb9SElaine Zhang #define OSC_HZ (24 * MHz) 15a5a5ddb9SElaine Zhang 16*76534374SZiyuan Xu #ifdef CONFIG_SPL_KERNEL_BOOT 17*76534374SZiyuan Xu #define APLL_HZ (1104 * MHz) 18*76534374SZiyuan Xu #else 19a5a5ddb9SElaine Zhang #define APLL_HZ (816 * MHz) 20*76534374SZiyuan Xu #endif 21a5a5ddb9SElaine Zhang #define GPLL_HZ (1188 * MHz) 22a5a5ddb9SElaine Zhang #define CPLL_HZ (1000 * MHz) 23a5a5ddb9SElaine Zhang 24a5a5ddb9SElaine Zhang /* RV1106 pll id */ 25a5a5ddb9SElaine Zhang enum rv1106_pll_id { 26a5a5ddb9SElaine Zhang APLL, 27a5a5ddb9SElaine Zhang DPLL, 28a5a5ddb9SElaine Zhang CPLL, 29a5a5ddb9SElaine Zhang GPLL, 30a5a5ddb9SElaine Zhang PLL_COUNT, 31a5a5ddb9SElaine Zhang }; 32a5a5ddb9SElaine Zhang 33a5a5ddb9SElaine Zhang struct rv1106_clk_info { 34a5a5ddb9SElaine Zhang unsigned long id; 35a5a5ddb9SElaine Zhang char *name; 36a5a5ddb9SElaine Zhang bool is_cru; 37a5a5ddb9SElaine Zhang }; 38a5a5ddb9SElaine Zhang 39a5a5ddb9SElaine Zhang struct rv1106_clk_priv { 40a5a5ddb9SElaine Zhang struct rv1106_cru *cru; 41a5a5ddb9SElaine Zhang struct rv1106_grf *grf; 42a5a5ddb9SElaine Zhang ulong gpll_hz; 43a5a5ddb9SElaine Zhang ulong cpll_hz; 44a5a5ddb9SElaine Zhang ulong armclk_hz; 45a5a5ddb9SElaine Zhang ulong armclk_enter_hz; 46a5a5ddb9SElaine Zhang ulong armclk_init_hz; 47a5a5ddb9SElaine Zhang bool sync_kernel; 48a5a5ddb9SElaine Zhang bool set_armclk_rate; 49a5a5ddb9SElaine Zhang }; 50a5a5ddb9SElaine Zhang 5132914815SElaine Zhang struct rv1106_grf_clk_priv { 5232914815SElaine Zhang struct rv1106_grf *grf; 5332914815SElaine Zhang }; 5432914815SElaine Zhang 55a5a5ddb9SElaine Zhang struct rv1106_pll { 56a5a5ddb9SElaine Zhang unsigned int con0; 57a5a5ddb9SElaine Zhang unsigned int con1; 58a5a5ddb9SElaine Zhang unsigned int con2; 59a5a5ddb9SElaine Zhang unsigned int con3; 60a5a5ddb9SElaine Zhang unsigned int con4; 61a5a5ddb9SElaine Zhang unsigned int reserved0[3]; 62a5a5ddb9SElaine Zhang }; 63a5a5ddb9SElaine Zhang 64a5a5ddb9SElaine Zhang struct rv1106_cru { 65a5a5ddb9SElaine Zhang unsigned int reserved0[192]; 66a5a5ddb9SElaine Zhang unsigned int pmu_clksel_con[8]; 67a5a5ddb9SElaine Zhang unsigned int reserved1[312]; 68a5a5ddb9SElaine Zhang unsigned int pmu_clkgate_con[3]; 69a5a5ddb9SElaine Zhang unsigned int reserved2[125]; 70a5a5ddb9SElaine Zhang unsigned int pmu_softrst_con[3]; 71a5a5ddb9SElaine Zhang unsigned int reserved3[15741]; 72a5a5ddb9SElaine Zhang struct rv1106_pll pll[4]; 73a5a5ddb9SElaine Zhang unsigned int reserved4[128]; 74a5a5ddb9SElaine Zhang unsigned int mode; 75a5a5ddb9SElaine Zhang unsigned int reserved5[31]; 76a5a5ddb9SElaine Zhang unsigned int clksel_con[34]; 77a5a5ddb9SElaine Zhang unsigned int reserved6[286]; 78a5a5ddb9SElaine Zhang unsigned int clkgate_con[4]; 79a5a5ddb9SElaine Zhang unsigned int reserved7[124]; 80a5a5ddb9SElaine Zhang unsigned int softrst_con[3]; 81a5a5ddb9SElaine Zhang unsigned int reserved8[125]; 82a5a5ddb9SElaine Zhang unsigned int glb_cnt_th; 83a5a5ddb9SElaine Zhang unsigned int glb_rst_st; 84a5a5ddb9SElaine Zhang unsigned int glb_srst_fst; 85a5a5ddb9SElaine Zhang unsigned int glb_srst_snd; 86a5a5ddb9SElaine Zhang unsigned int glb_rst_con; 87a5a5ddb9SElaine Zhang unsigned int con[2]; 88a5a5ddb9SElaine Zhang unsigned int sdmmc_con[2]; 89a5a5ddb9SElaine Zhang unsigned int emmc_con[2]; 90a5a5ddb9SElaine Zhang unsigned int reserved9[1461]; 91a5a5ddb9SElaine Zhang unsigned int peri_clksel_con[12]; 92a5a5ddb9SElaine Zhang unsigned int reserved10[308]; 93a5a5ddb9SElaine Zhang unsigned int peri_clkgate_con[8]; 94a5a5ddb9SElaine Zhang unsigned int reserved11[120]; 95a5a5ddb9SElaine Zhang unsigned int peri_softrst_con[8]; 96a5a5ddb9SElaine Zhang unsigned int reserved12[1592]; 97a5a5ddb9SElaine Zhang unsigned int vi_clksel_con[4]; 98a5a5ddb9SElaine Zhang unsigned int reserved13[316]; 99a5a5ddb9SElaine Zhang unsigned int vi_clkgate_con[3]; 100a5a5ddb9SElaine Zhang unsigned int reserved14[125]; 101a5a5ddb9SElaine Zhang unsigned int vi_softrst_con[3]; 10275bf999aSElaine Zhang unsigned int reserved15[3645]; 10375bf999aSElaine Zhang unsigned int core_clksel_con[5]; 10475bf999aSElaine Zhang unsigned int reserved16[2043]; 105a5a5ddb9SElaine Zhang unsigned int vepu_clksel_con[2]; 10675bf999aSElaine Zhang unsigned int reserved17[318]; 107a5a5ddb9SElaine Zhang unsigned int vepu_clkgate_con[3]; 10875bf999aSElaine Zhang unsigned int reserved18[125]; 109a5a5ddb9SElaine Zhang unsigned int vepu_softrst_con[2]; 11075bf999aSElaine Zhang unsigned int reserved19[1598]; 111a5a5ddb9SElaine Zhang unsigned int vo_clksel_con[4]; 11275bf999aSElaine Zhang unsigned int reserved20[316]; 113a5a5ddb9SElaine Zhang unsigned int vo_clkgate_con[3]; 11475bf999aSElaine Zhang unsigned int reserved21[125]; 115a5a5ddb9SElaine Zhang unsigned int vo_softrst_con[4]; 116a5a5ddb9SElaine Zhang }; 117a5a5ddb9SElaine Zhang check_member(rv1106_cru, vo_softrst_con[0], 0x1ca00); 118a5a5ddb9SElaine Zhang 119a5a5ddb9SElaine Zhang struct pll_rate_table { 120a5a5ddb9SElaine Zhang unsigned long rate; 121a5a5ddb9SElaine Zhang unsigned int fbdiv; 122a5a5ddb9SElaine Zhang unsigned int postdiv1; 123a5a5ddb9SElaine Zhang unsigned int refdiv; 124a5a5ddb9SElaine Zhang unsigned int postdiv2; 125a5a5ddb9SElaine Zhang unsigned int dsmpd; 126a5a5ddb9SElaine Zhang unsigned int frac; 127a5a5ddb9SElaine Zhang }; 128a5a5ddb9SElaine Zhang 129a5a5ddb9SElaine Zhang #define RV1106_TOPCRU_BASE 0x10000 130a5a5ddb9SElaine Zhang #define RV1106_SUBDDRCRU_BASE 0x1F000 131a5a5ddb9SElaine Zhang 132a5a5ddb9SElaine Zhang #define RV1106_PLL_CON(x) ((x) * 0x4 + RV1106_TOPCRU_BASE) 133a5a5ddb9SElaine Zhang #define RV1106_MODE_CON (0x280 + RV1106_TOPCRU_BASE) 134a5a5ddb9SElaine Zhang #define RV1106_SUBDDRMODE_CON (0x280 + RV1106_SUBDDRCRU_BASE) 135a5a5ddb9SElaine Zhang 136a5a5ddb9SElaine Zhang enum { 137a5a5ddb9SElaine Zhang /* CRU_PMU_CLK_SEL0_CON */ 138a5a5ddb9SElaine Zhang CLK_I2C1_SEL_SHIFT = 6, 139a5a5ddb9SElaine Zhang CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 140a5a5ddb9SElaine Zhang CLK_I2C1_SEL_200M = 0, 141a5a5ddb9SElaine Zhang CLK_I2C1_SEL_100M, 142a5a5ddb9SElaine Zhang CLK_I2C1_SEL_24M, 143a5a5ddb9SElaine Zhang CLK_I2C1_SEL_32K, 144a5a5ddb9SElaine Zhang HCLK_PMU_SEL_SHIFT = 4, 145a5a5ddb9SElaine Zhang HCLK_PMU_SEL_MASK = 0x3 << HCLK_PMU_SEL_SHIFT, 146a5a5ddb9SElaine Zhang HCLK_PMU_SEL_200M = 0, 147a5a5ddb9SElaine Zhang HCLK_PMU_SEL_100M, 148a5a5ddb9SElaine Zhang HCLK_PMU_SEL_24M, 149a5a5ddb9SElaine Zhang PCLK_PMU_SEL_SHIFT = 3, 150a5a5ddb9SElaine Zhang PCLK_PMU_SEL_MASK = 0x1 << PCLK_PMU_SEL_SHIFT, 151a5a5ddb9SElaine Zhang PCLK_PMU_SEL_100M = 0, 152a5a5ddb9SElaine Zhang PCLK_PMU_SEL_24M, 153a5a5ddb9SElaine Zhang 154a5a5ddb9SElaine Zhang /* CRU_CLK_SEL5_CON */ 155a5a5ddb9SElaine Zhang CLK_UART_SRC_SEL_SHIFT = 5, 156a5a5ddb9SElaine Zhang CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 157a5a5ddb9SElaine Zhang CLK_UART_SRC_SEL_GPLL = 0, 158a5a5ddb9SElaine Zhang CLK_UART_SRC_SEL_CPLL, 159a5a5ddb9SElaine Zhang CLK_UART_SRC_DIV_SHIFT = 0, 160a5a5ddb9SElaine Zhang CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT, 161a5a5ddb9SElaine Zhang 162a5a5ddb9SElaine Zhang /* CRU_CLK_SEL6_CON */ 163a5a5ddb9SElaine Zhang CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 164a5a5ddb9SElaine Zhang CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 165a5a5ddb9SElaine Zhang CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 166a5a5ddb9SElaine Zhang CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 167a5a5ddb9SElaine Zhang 168a5a5ddb9SElaine Zhang /* CRU_CLK_SEL7_CON */ 169a5a5ddb9SElaine Zhang CLK_UART_SEL_SHIFT = 0, 170a5a5ddb9SElaine Zhang CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 171a5a5ddb9SElaine Zhang CLK_UART_SEL_SRC = 0, 172a5a5ddb9SElaine Zhang CLK_UART_SEL_FRAC, 173a5a5ddb9SElaine Zhang CLK_UART_SEL_XIN24M, 174a5a5ddb9SElaine Zhang 175a5a5ddb9SElaine Zhang /* CRU_CLK_SEL23_CON */ 176a5a5ddb9SElaine Zhang DCLK_VOP_SEL_SHIFT = 8, 177a5a5ddb9SElaine Zhang DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, 178a5a5ddb9SElaine Zhang DCLK_VOP_SEL_GPLL = 0, 179a5a5ddb9SElaine Zhang DCLK_VOP_SEL_CPLL, 180a5a5ddb9SElaine Zhang DCLK_VOP_DIV_SHIFT = 3, 181a5a5ddb9SElaine Zhang DCLK_VOP_DIV_MASK = 0x1f << DCLK_VOP_DIV_SHIFT, 182a5a5ddb9SElaine Zhang 183a5a5ddb9SElaine Zhang /* CRU_CLK_SEL24_CON */ 184a5a5ddb9SElaine Zhang PCLK_TOP_SEL_SHIFT = 5, 185a5a5ddb9SElaine Zhang PCLK_TOP_SEL_MASK = 0x3 << PCLK_TOP_SEL_SHIFT, 186a5a5ddb9SElaine Zhang PCLK_TOP_SEL_100M = 0, 187a5a5ddb9SElaine Zhang PCLK_TOP_SEL_50M, 188a5a5ddb9SElaine Zhang PCLK_TOP_SEL_24M, 189a5a5ddb9SElaine Zhang 190a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL1_CON */ 191a5a5ddb9SElaine Zhang CLK_I2C3_SEL_SHIFT = 14, 192a5a5ddb9SElaine Zhang CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, 193a5a5ddb9SElaine Zhang CLK_I2C2_SEL_SHIFT = 12, 194a5a5ddb9SElaine Zhang CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 195a5a5ddb9SElaine Zhang CLK_I2C0_SEL_SHIFT = 8, 196a5a5ddb9SElaine Zhang CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 197a5a5ddb9SElaine Zhang CLK_I2C0_SEL_200M = 0, 198a5a5ddb9SElaine Zhang CLK_I2C0_SEL_100M, 199a5a5ddb9SElaine Zhang CLK_I2C0_SEL_50M, 200a5a5ddb9SElaine Zhang CLK_I2C0_SEL_24M, 201a5a5ddb9SElaine Zhang HCLK_PERI_SEL_SHIFT = 4, 202a5a5ddb9SElaine Zhang HCLK_PERI_SEL_MASK = 0x3 << HCLK_PERI_SEL_SHIFT, 203a5a5ddb9SElaine Zhang HCLK_PERI_SEL_200M = 0, 204a5a5ddb9SElaine Zhang HCLK_PERI_SEL_100M, 205a5a5ddb9SElaine Zhang HCLK_PERI_SEL_50M, 206a5a5ddb9SElaine Zhang HCLK_PERI_SEL_24M, 207a5a5ddb9SElaine Zhang ACLK_PERI_SEL_SHIFT = 2, 208a5a5ddb9SElaine Zhang ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT, 209a5a5ddb9SElaine Zhang ACLK_PERI_SEL_400M = 0, 210a5a5ddb9SElaine Zhang ACLK_PERI_SEL_200M, 211a5a5ddb9SElaine Zhang ACLK_PERI_SEL_100M, 212a5a5ddb9SElaine Zhang ACLK_PERI_SEL_24M, 213a5a5ddb9SElaine Zhang PCLK_PERI_SEL_SHIFT = 0, 214a5a5ddb9SElaine Zhang PCLK_PERI_SEL_MASK = 0x3 << PCLK_PERI_SEL_SHIFT, 215a5a5ddb9SElaine Zhang PCLK_PERI_SEL_100M = 0, 216a5a5ddb9SElaine Zhang PCLK_PERI_SEL_50M, 217a5a5ddb9SElaine Zhang PCLK_PERI_SEL_24M, 218a5a5ddb9SElaine Zhang 219a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL2_CON */ 220a5a5ddb9SElaine Zhang CLK_I2C4_SEL_SHIFT = 0, 221a5a5ddb9SElaine Zhang CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, 222a5a5ddb9SElaine Zhang 223a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL6_CON */ 224a5a5ddb9SElaine Zhang CLK_PWM2_SEL_SHIFT = 11, 225a5a5ddb9SElaine Zhang CLK_PWM2_SEL_MASK = 0x3 << CLK_PWM2_SEL_SHIFT, 226a5a5ddb9SElaine Zhang CLK_PWM1_SEL_SHIFT = 9, 227a5a5ddb9SElaine Zhang CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 228a5a5ddb9SElaine Zhang CLK_PWM_SEL_100M = 0, 229a5a5ddb9SElaine Zhang CLK_PWM_SEL_50M, 230a5a5ddb9SElaine Zhang CLK_PWM_SEL_24M, 231a5a5ddb9SElaine Zhang CLK_PKA_CRYPTO_SEL_SHIFT = 7, 232a5a5ddb9SElaine Zhang CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 233a5a5ddb9SElaine Zhang CLK_CORE_CRYPTO_SEL_SHIFT = 5, 234a5a5ddb9SElaine Zhang CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 235a5a5ddb9SElaine Zhang CLK_CRYPTO_SEL_300M = 0, 236a5a5ddb9SElaine Zhang CLK_CRYPTO_SEL_200M, 237a5a5ddb9SElaine Zhang CLK_CRYPTO_SEL_100M, 238a5a5ddb9SElaine Zhang CLK_CRYPTO_SEL_24M, 239a5a5ddb9SElaine Zhang CLK_SARADC_DIV_SHIFT = 0, 240a5a5ddb9SElaine Zhang CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 241a5a5ddb9SElaine Zhang CLK_SPI1_SEL_SHIFT = 3, 242a5a5ddb9SElaine Zhang CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 243a5a5ddb9SElaine Zhang 244a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL7_CON */ 245b81ef8b2SElaine Zhang DCLK_DECOM_SEL_SHIFT = 14, 246b81ef8b2SElaine Zhang DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT, 247b81ef8b2SElaine Zhang DCLK_DECOM_SEL_400M = 0, 248b81ef8b2SElaine Zhang DCLK_DECOM_SEL_200M, 249b81ef8b2SElaine Zhang DCLK_DECOM_SEL_100M, 250b81ef8b2SElaine Zhang DCLK_DECOM_SEL_24M, 251a5a5ddb9SElaine Zhang CLK_SFC_SEL_SHIFT = 12, 252a5a5ddb9SElaine Zhang CLK_SFC_SEL_MASK = 0x3 << CLK_SFC_SEL_SHIFT, 253a5a5ddb9SElaine Zhang CLK_SFC_SEL_500M = 0, 254a5a5ddb9SElaine Zhang CLK_SFC_SEL_300M, 255a5a5ddb9SElaine Zhang CLK_SFC_SEL_200M, 256a5a5ddb9SElaine Zhang CLK_SFC_SEL_24M, 257a5a5ddb9SElaine Zhang CLK_SFC_DIV_SHIFT = 7, 258a5a5ddb9SElaine Zhang CLK_SFC_DIV_MASK = 0x1f << CLK_SFC_DIV_SHIFT, 259a5a5ddb9SElaine Zhang CLK_EMMC_SEL_SHIFT = 6, 260a5a5ddb9SElaine Zhang CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT, 261a5a5ddb9SElaine Zhang CLK_MMC_SEL_400M = 0, 262a5a5ddb9SElaine Zhang CLK_MMC_SEL_24M, 263a5a5ddb9SElaine Zhang CLK_EMMC_DIV_SHIFT = 0, 264a5a5ddb9SElaine Zhang CLK_EMMC_DIV_MASK = 0x3f << CLK_EMMC_DIV_SHIFT, 265a5a5ddb9SElaine Zhang 266a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL9_CON */ 267a5a5ddb9SElaine Zhang ACLK_BUS_SEL_SHIFT = 0, 268a5a5ddb9SElaine Zhang ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 269a5a5ddb9SElaine Zhang ACLK_BUS_SEL_300M = 0, 270a5a5ddb9SElaine Zhang ACLK_BUS_SEL_200M, 271a5a5ddb9SElaine Zhang ACLK_BUS_SEL_100M, 272a5a5ddb9SElaine Zhang ACLK_BUS_SEL_24M, 273a5a5ddb9SElaine Zhang 274a5a5ddb9SElaine Zhang /* CRU_PERI_CLK_SEL11_CON */ 275a5a5ddb9SElaine Zhang CLK_PWM0_SEL_SHIFT = 0, 276a5a5ddb9SElaine Zhang CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, 277a5a5ddb9SElaine Zhang 278a5a5ddb9SElaine Zhang /* CRU_VEPU_CLK_SEL0_CON */ 279a5a5ddb9SElaine Zhang CLK_SPI0_SEL_SHIFT = 12, 280a5a5ddb9SElaine Zhang CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 281a5a5ddb9SElaine Zhang CLK_SPI0_SEL_200M = 0, 282a5a5ddb9SElaine Zhang CLK_SPI0_SEL_100M, 283a5a5ddb9SElaine Zhang CLK_SPI0_SEL_50M, 284a5a5ddb9SElaine Zhang CLK_SPI0_SEL_24M, 285a5a5ddb9SElaine Zhang 28675bf999aSElaine Zhang /* CRU_CORE_CLK_SEL0_CON */ 28775bf999aSElaine Zhang CLK_CORE_DIV_SHIFT = 0, 28875bf999aSElaine Zhang CLK_CORE_DIV_MASK = 0x1f << CLK_CORE_DIV_SHIFT, 28975bf999aSElaine Zhang 290a5a5ddb9SElaine Zhang /* CRU_VI_CLK_SEL1_CON */ 291a5a5ddb9SElaine Zhang CLK_SDMMC_SEL_SHIFT = 14, 292a5a5ddb9SElaine Zhang CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT, 293a5a5ddb9SElaine Zhang CLK_SDMMC_DIV_SHIFT = 8, 294a5a5ddb9SElaine Zhang CLK_SDMMC_DIV_MASK = 0x3f << CLK_SDMMC_DIV_SHIFT, 295a5a5ddb9SElaine Zhang 296a5a5ddb9SElaine Zhang /* CRU_VO_CLK_SEL1_CON */ 297a5a5ddb9SElaine Zhang ACLK_VOP_SEL_SHIFT = 10, 298a5a5ddb9SElaine Zhang ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT, 299a5a5ddb9SElaine Zhang ACLK_VOP_SEL_300M = 0, 300a5a5ddb9SElaine Zhang ACLK_VOP_SEL_200M, 301a5a5ddb9SElaine Zhang ACLK_VOP_SEL_100M, 302a5a5ddb9SElaine Zhang ACLK_VOP_SEL_24M, 303a5a5ddb9SElaine Zhang 304a5a5ddb9SElaine Zhang /* CRU_VO_CLK_SEL3_CON */ 305a5a5ddb9SElaine Zhang CLK_TSADC_TSEN_DIV_SHIFT = 5, 306a5a5ddb9SElaine Zhang CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, 307a5a5ddb9SElaine Zhang CLK_TSADC_DIV_SHIFT = 0, 308a5a5ddb9SElaine Zhang CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, 309a5a5ddb9SElaine Zhang }; 310a5a5ddb9SElaine Zhang #endif 311