| #
28e9e98a |
| 17-Feb-2020 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: Id356c87b1db158a0638e4560e886
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: Id356c87b1db158a0638e4560e886868f133dfaf9
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
show more ...
|
| #
a9f7ad7f |
| 25-Sep-2019 |
Jason Zhu <jason.zhu@rock-chips.com> |
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: I28f56f161eb40cf640f7d979f53f
clk: rockchip: rk1808: set gpll to 594000000
The eMMC clk is depended on gpll, and the eMMC is needed to run 150MHz
in HS200 mode. So set gpll to 594000000.
Change-Id: I28f56f161eb40cf640f7d979f53f8e6fdaff957c
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
show more ...
|
| #
32f0452d |
| 01-Jul-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: support crypto clk get/set rate
Change-Id: Id09bd7e6a303bc3e72421aeef277a16805e95761
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
b9f59722 |
| 14-Mar-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: add mac clk interface
support mac clk set rate and set parent.
Change-Id: I3b4626fd3fcc5ffdf3c58add9c1bc002bb56429a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
ed6f5d94 |
| 22-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: print arm enter and init rate
Change-Id: I14f0b0c95b1367266fe9c64050a602ad58208d53
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
| #
08b717ab |
| 22-Nov-2018 |
Lin Huang <hl@rock-chips.com> |
clk: rockchip: rk1808: set apll default frequency to 1.2GHz
For cpu_vdd default voltage enough to support cpu frequency to 1.2GHz,
so set rk1808 default cpu frequency to 1.2GHz.
Change-Id: Ia8a888e
clk: rockchip: rk1808: set apll default frequency to 1.2GHz
For cpu_vdd default voltage enough to support cpu frequency to 1.2GHz,
so set rk1808 default cpu frequency to 1.2GHz.
Change-Id: Ia8a888ee79ab3ae3868790bcc1851552acf90086
Signed-off-by: Lin Huang <hl@rock-chips.com>
show more ...
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| #
1ae6d6e5 |
| 10-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: fix up the dclk_raw/lite set rate error
Change-Id: I0b8c7d0e15501c7ecc3c5acb0e0844e722ad18ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
dad14895 |
| 06-Oct-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: rk1808: support pclk_pmu freq setting
set pclk_pmu freq before ppll freq setting.
Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chi
clk: rockchip: rk1808: support pclk_pmu freq setting
set pclk_pmu freq before ppll freq setting.
Change-Id: Ieab142dd9e41d98d9798be08a0f01f941d3ad9a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
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| #
45a3782a |
| 06-Aug-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9
rockchip: clk: rk1808: add clk driver for rk1808
Add basic clock for rk1808 which including pll, cpu, bus,
emmc, i2c, spi, pwm, saradc clock init.
Change-Id: I302c91e64d0c44ea991d734371811ab4be77c9ab
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
show more ...
|