| #
89cc3f4d |
| 10-Aug-2021 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: px30: add otp clk and support px30s
Change-Id: I4e16a4e28a25ce3897a368a35da560faf8264640
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
1a4f6af8 |
| 02-Mar-2020 |
Joseph Chen <chenjh@rock-chips.com> |
Merge branch 'next-dev' into thunder-boot
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| #
e82920f3 |
| 18-Nov-2019 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: px30: Enable support for UART5
Because the UART2 IOs are mux with SDcard, in order to use SDCard,
we need to use UART5(on evb RPi connector) instead of UART2M0
Change-Id: Ibeab51636eb748f
rockchip: px30: Enable support for UART5
Because the UART2 IOs are mux with SDcard, in order to use SDCard,
we need to use UART5(on evb RPi connector) instead of UART2M0
Change-Id: Ibeab51636eb748f389d9211193c0b5682c266c9e
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
show more ...
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| #
dfce0096 |
| 22-Jan-2019 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: px30: print arm enter and init rate
Change-Id: I0d2a1c6bb92397210314322fd147c4a8a6e81abd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
51d1c6b1 |
| 11-Dec-2018 |
Elaine Zhang <zhangqing@rock-chips.com> |
clk: rockchip: px30: support crypto clk setting
Change-Id: I9971fb2b6a40640d78fb259c72aac32582f8e90d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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| #
95f26412 |
| 21-Sep-2018 |
Sugar Zhang <sugar.zhang@rock-chips.com> |
clk: rockchip: px30: add support clock for SCLK_I2S1
Change-Id: Iaaacd6fdabe2c702202ffe09dc95cd6d648597d6
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
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| #
45484bdc |
| 15-Aug-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add support to initialize npll rate
Change-Id: If98ed54ad785a40efae7da78c5f0122158a3de61
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
c996ae8a |
| 06-Aug-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add support to get vopl aclk and dclk
Change-Id: Id40cbddf780889e308839b7beb2cfb894d407914
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
fe784db3 |
| 06-Aug-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add px30_clk_init()
Add support to initialize gpll, bus and peri clock rate.
Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-c
rockchip: clk: px30: Add px30_clk_init()
Add support to initialize gpll, bus and peri clock rate.
Change-Id: I84f496094606ac2231ea27ad9072b079c45f9f94
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
show more ...
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| #
d101530a |
| 03-Aug-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add support to set vopl aclk and dclk rate
Change-Id: I31376ebb8d1d40d46ad4e2b6421b65ac7fae096d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
0f72a325 |
| 06-Jul-2018 |
YouMin Chen <cym@rock-chips.com> |
rockchip: px30: add UART clock and iomux for TPL_BUILD
Change-Id: Id2fed3e99e0e421063e006fcf857fed889216b72
Signed-off-by: YouMin Chen <cym@rock-chips.com>
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| #
37428b92 |
| 23-Mar-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add support to set and get armclk rate
Change-Id: I40948e5cedb781cad7129b02dfbf34fecb8689ca
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
dd472d4f |
| 21-Jun-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Change apll rate to 600MHz
The initial voltage may be too low for 816MHz and it is enough for
600MHz.
Change-Id: Ifa1438d8d3056c9fb8fb3e578a28c26682a27e46
Signed-off-by: Finley
rockchip: clk: px30: Change apll rate to 600MHz
The initial voltage may be too low for 816MHz and it is enough for
600MHz.
Change-Id: Ifa1438d8d3056c9fb8fb3e578a28c26682a27e46
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
show more ...
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| #
7a1915c0 |
| 22-Mar-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: px30: implement soc_clk_dump
Change-Id: I8c5c4468ed6c6d1f4767a0a6ddaa2b47037fe8bc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
cefa5186 |
| 06-Jun-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: px30: Add support for pmucru
Change-Id: I445ae2b2491d1709d2790412fcc07dccf56189d9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
0dc8896c |
| 09-Mar-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: clk: px30: only do one time clk init
We may get into clk_probe more than one time from TPL/SPL/U-Boot,
and we only need to init bus clock one time.
Change-Id: Iab0434c66d344ff57c1edd30679
rockchip: clk: px30: only do one time clk init
We may get into clk_probe more than one time from TPL/SPL/U-Boot,
and we only need to init bus clock one time.
Change-Id: Iab0434c66d344ff57c1edd30679c3ab3bb8f2b17
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
show more ...
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| #
30f1f38d |
| 23-Feb-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: px30: Add support to set and get rate for vopb
Change-Id: I5105c4823ffd6632c29a8faa80b995f7ef0decaa
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
77ecce68 |
| 25-Feb-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: px30: Modify gpll to 1200MHz
Change-Id: Ia853acdc1d6c7085712379680b6fb1ed6a5802d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
db235eb5 |
| 23-Feb-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
clk: rockchip: px30: Move pll mode operation into rkclk_set_pll
Change-Id: I55bc3f9eedd41c40b8e424b482ad620b248262b1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
f67f522b |
| 05-Feb-2018 |
Finley Xiao <finley.xiao@rock-chips.com> |
rockchip: clk: px30: Add support for i2c, pwm, spi and saradc
Change-Id: I81e1bf5776952da62dcdc7fdf58587ba0ddf20ae
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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| #
89f991f8 |
| 06-Feb-2018 |
Joseph Chen <chenjh@rock-chips.com> |
rockchip: px30: fix clk and pmugrf issue
Change-Id: I481abacc5f69e645b4b3ca2cc5b27bf6cc3a6ca7
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
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| #
a60961a3 |
| 22-Jan-2018 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: px30: add clock driver
Add basic clock for px30 which including cpu, bus, emmc clock init.
Change-Id: I43a1eaee20bda330ce4ff0556b3fda14a0451681
Signed-off-by: Kever Yang <kever.yang@rock-
rockchip: px30: add clock driver
Add basic clock for px30 which including cpu, bus, emmc clock init.
Change-Id: I43a1eaee20bda330ce4ff0556b3fda14a0451681
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
show more ...
|