1b991d4b5SXuhui Lin /* SPDX-License-Identifier: GPL-2.0 */ 2b991d4b5SXuhui Lin /* 3b991d4b5SXuhui Lin * Copyright (c) 2025 Rockchip Electronics Co. Ltd. 4b991d4b5SXuhui Lin * Author: Elaine Zhang <zhangqing@rock-chips.com> 5b991d4b5SXuhui Lin */ 6b991d4b5SXuhui Lin 7b991d4b5SXuhui Lin #ifndef _ASM_ARCH_CRU_RV1126B_H 8b991d4b5SXuhui Lin #define _ASM_ARCH_CRU_RV1126B_H 9b991d4b5SXuhui Lin 10b991d4b5SXuhui Lin #include <common.h> 11b991d4b5SXuhui Lin 12b991d4b5SXuhui Lin #define MHz 1000000 13b991d4b5SXuhui Lin #define KHz 1000 14b991d4b5SXuhui Lin #define OSC_HZ (24 * MHz) 15b991d4b5SXuhui Lin #define RC_OSC_HZ (125 * MHz) 16b991d4b5SXuhui Lin 17b991d4b5SXuhui Lin #define GPLL_HZ (1188 * MHz) 18b991d4b5SXuhui Lin #define AUPLL_HZ (983040000) 19b991d4b5SXuhui Lin #define CPLL_HZ (1000 * MHz) 20b991d4b5SXuhui Lin 21b991d4b5SXuhui Lin /* RV1126B pll id */ 22b991d4b5SXuhui Lin enum rv1126b_pll_id { 23b991d4b5SXuhui Lin GPLL, 24b991d4b5SXuhui Lin AUPLL, 25b991d4b5SXuhui Lin CPLL, 26b991d4b5SXuhui Lin PLL_COUNT, 27b991d4b5SXuhui Lin }; 28b991d4b5SXuhui Lin 29b991d4b5SXuhui Lin struct rv1126b_clk_info { 30b991d4b5SXuhui Lin unsigned long id; 31b991d4b5SXuhui Lin char *name; 32b991d4b5SXuhui Lin bool is_cru; 33b991d4b5SXuhui Lin }; 34b991d4b5SXuhui Lin 35b991d4b5SXuhui Lin struct rv1126b_clk_priv { 36b991d4b5SXuhui Lin struct rv1126b_cru *cru; 37b991d4b5SXuhui Lin struct rv1126b_grf *grf; 38b991d4b5SXuhui Lin ulong gpll_hz; 39b991d4b5SXuhui Lin ulong aupll_hz; 40b991d4b5SXuhui Lin ulong cpll_hz; 41b991d4b5SXuhui Lin ulong armclk_hz; 42b991d4b5SXuhui Lin ulong armclk_enter_hz; 43b991d4b5SXuhui Lin ulong armclk_init_hz; 44b991d4b5SXuhui Lin bool sync_kernel; 45b991d4b5SXuhui Lin bool set_armclk_rate; 46b991d4b5SXuhui Lin }; 47b991d4b5SXuhui Lin 48b991d4b5SXuhui Lin struct rv1126b_grf_clk_priv { 49b991d4b5SXuhui Lin struct rv1126b_grf *grf; 50b991d4b5SXuhui Lin }; 51b991d4b5SXuhui Lin 52b991d4b5SXuhui Lin struct rv1126b_pll { 53b991d4b5SXuhui Lin unsigned int con0; 54b991d4b5SXuhui Lin unsigned int con1; 55b991d4b5SXuhui Lin unsigned int con2; 56b991d4b5SXuhui Lin unsigned int con3; 57b991d4b5SXuhui Lin unsigned int con4; 58b991d4b5SXuhui Lin unsigned int reserved0[3]; 59b991d4b5SXuhui Lin }; 60b991d4b5SXuhui Lin 61b991d4b5SXuhui Lin struct rv1126b_cru { 62b991d4b5SXuhui Lin struct rv1126b_pll pll[2]; 63b991d4b5SXuhui Lin unsigned int reserved0[176]; 64b991d4b5SXuhui Lin unsigned int clksel_con[71]; 65b991d4b5SXuhui Lin unsigned int reserved1[249]; 66b991d4b5SXuhui Lin unsigned int clkgate_con[16]; 67b991d4b5SXuhui Lin unsigned int reserved2[112]; 68b991d4b5SXuhui Lin unsigned int softrst_con[16]; 69b991d4b5SXuhui Lin unsigned int reserved3[112]; 70b991d4b5SXuhui Lin unsigned int glb_cnt_th; 71b991d4b5SXuhui Lin unsigned int glb_rst_st; 72b991d4b5SXuhui Lin unsigned int glb_srst_fst; 73b991d4b5SXuhui Lin unsigned int glb_srst_snd; 74b991d4b5SXuhui Lin unsigned int glb_rst_con[3]; 75b991d4b5SXuhui Lin unsigned int reserved4[41]; 76b991d4b5SXuhui Lin unsigned int clk_cm_frac0_div_h; 77b991d4b5SXuhui Lin unsigned int clk_cm_frac1_div_h; 78b991d4b5SXuhui Lin unsigned int clk_cm_frac2_div_h; 79b991d4b5SXuhui Lin unsigned int clk_uart_frac0_div_h; 80b991d4b5SXuhui Lin unsigned int clk_uart_frac1_div_h; 81b991d4b5SXuhui Lin unsigned int clk_audio_frac0_div_h; 82b991d4b5SXuhui Lin unsigned int clk_audio_frac1_div_h; 83b991d4b5SXuhui Lin unsigned int reserved5[15753]; 84b991d4b5SXuhui Lin unsigned int bus_clksel_con[4]; 85b991d4b5SXuhui Lin unsigned int reserved6[316]; 86b991d4b5SXuhui Lin unsigned int bus_clkgate_con[7]; 87b991d4b5SXuhui Lin unsigned int reserved7[121]; 88b991d4b5SXuhui Lin unsigned int bus_softrst_con[8]; 89b991d4b5SXuhui Lin unsigned int reserved8[15928]; 90b991d4b5SXuhui Lin unsigned int peri_clksel_con[2]; 91b991d4b5SXuhui Lin unsigned int reserved9[318]; 92b991d4b5SXuhui Lin unsigned int peri_clkgate_con[2]; 93b991d4b5SXuhui Lin unsigned int reserved10[126]; 94b991d4b5SXuhui Lin unsigned int peri_softrst_con[2]; 95b991d4b5SXuhui Lin unsigned int reserved11[15934]; 96b991d4b5SXuhui Lin unsigned int core_clksel_con[3]; 97b991d4b5SXuhui Lin unsigned int reserved12[317]; 98b991d4b5SXuhui Lin unsigned int core_clkgate_con[2]; 99b991d4b5SXuhui Lin unsigned int reserved13[126]; 100b991d4b5SXuhui Lin unsigned int core_softrst_con[2]; 101b991d4b5SXuhui Lin unsigned int reserved14[15934]; 102b991d4b5SXuhui Lin unsigned int pmu_clksel_con[9]; 103b991d4b5SXuhui Lin unsigned int reserved15[311]; 104b991d4b5SXuhui Lin unsigned int pmu_clkgate_con[4]; 105b991d4b5SXuhui Lin unsigned int reserved16[124]; 106b991d4b5SXuhui Lin unsigned int pmu_softrst_con[4]; 107b991d4b5SXuhui Lin unsigned int reserved17[15932]; 108b991d4b5SXuhui Lin unsigned int pmu1_clksel_con[2]; 109b991d4b5SXuhui Lin unsigned int reserved18[318]; 110b991d4b5SXuhui Lin unsigned int pmu1_clkgate_con[2]; 111b991d4b5SXuhui Lin unsigned int reserved19[126]; 112b991d4b5SXuhui Lin unsigned int pmu1_softrst_con[2]; 113b991d4b5SXuhui Lin unsigned int reserved20[32318]; 114b991d4b5SXuhui Lin unsigned int vi_clksel_con[1]; 115b991d4b5SXuhui Lin unsigned int reserved21[319]; 116b991d4b5SXuhui Lin unsigned int vi_clkgate_con[5]; 117b991d4b5SXuhui Lin unsigned int reserved22[123]; 118b991d4b5SXuhui Lin unsigned int vi_softrst_con[4]; 119b991d4b5SXuhui Lin }; 120b991d4b5SXuhui Lin 121b991d4b5SXuhui Lin check_member(rv1126b_cru, clksel_con[0], 0x300); 122b991d4b5SXuhui Lin check_member(rv1126b_cru, clkgate_con[0], 0x800); 123b991d4b5SXuhui Lin check_member(rv1126b_cru, softrst_con[0], 0xa00); 124b991d4b5SXuhui Lin check_member(rv1126b_cru, clk_cm_frac0_div_h, 0xcc0); 125b991d4b5SXuhui Lin check_member(rv1126b_cru, bus_clksel_con[0], 0x10300); 126b991d4b5SXuhui Lin check_member(rv1126b_cru, bus_clkgate_con[0], 0x10800); 127b991d4b5SXuhui Lin check_member(rv1126b_cru, bus_softrst_con[0], 0x10a00); 128b991d4b5SXuhui Lin check_member(rv1126b_cru, peri_clksel_con[0], 0x20300); 129b991d4b5SXuhui Lin check_member(rv1126b_cru, peri_clkgate_con[0], 0x20800); 130b991d4b5SXuhui Lin check_member(rv1126b_cru, peri_softrst_con[0], 0x20a00); 131b991d4b5SXuhui Lin check_member(rv1126b_cru, core_clksel_con[0], 0x30300); 132b991d4b5SXuhui Lin check_member(rv1126b_cru, core_clkgate_con[0], 0x30800); 133b991d4b5SXuhui Lin check_member(rv1126b_cru, core_softrst_con[0], 0x30a00); 134b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu_clksel_con[0], 0x40300); 135b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu_clkgate_con[0], 0x40800); 136b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu_softrst_con[0], 0x40a00); 137b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu1_clksel_con[0], 0x50300); 138b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu1_clkgate_con[0], 0x50800); 139b991d4b5SXuhui Lin check_member(rv1126b_cru, pmu1_softrst_con[0], 0x50a00); 140b991d4b5SXuhui Lin check_member(rv1126b_cru, vi_clksel_con[0], 0x70300); 141b991d4b5SXuhui Lin check_member(rv1126b_cru, vi_clkgate_con[0], 0x70800); 142b991d4b5SXuhui Lin check_member(rv1126b_cru, vi_softrst_con[0], 0x70a00); 143b991d4b5SXuhui Lin 144b991d4b5SXuhui Lin struct pll_rate_table { 145b991d4b5SXuhui Lin unsigned long rate; 146b991d4b5SXuhui Lin unsigned int fbdiv; 147b991d4b5SXuhui Lin unsigned int postdiv1; 148b991d4b5SXuhui Lin unsigned int refdiv; 149b991d4b5SXuhui Lin unsigned int postdiv2; 150b991d4b5SXuhui Lin unsigned int dsmpd; 151b991d4b5SXuhui Lin unsigned int frac; 152b991d4b5SXuhui Lin }; 153b991d4b5SXuhui Lin 154b991d4b5SXuhui Lin #define RV1126B_CRU_BASE 0x20000000 155b991d4b5SXuhui Lin #define RV1126B_TOPCRU_BASE 0x0 156b991d4b5SXuhui Lin #define RV1126B_BUSCRU_BASE 0x10000 157b991d4b5SXuhui Lin #define RV1126B_PERICRU_BASE 0x20000 158b991d4b5SXuhui Lin #define RV1126B_CORECRU_BASE 0x30000 159b991d4b5SXuhui Lin #define RV1126B_PMUCRU_BASE 0x40000 160b991d4b5SXuhui Lin #define RV1126B_PMU1CRU_BASE 0x50000 161b991d4b5SXuhui Lin #define RV1126B_DDRCRU_BASE 0x60000 162b991d4b5SXuhui Lin #define RV1126B_SUBDDRCRU_BASE 0x68000 163b991d4b5SXuhui Lin #define RV1126B_VICRU_BASE 0x70000 164b991d4b5SXuhui Lin #define RV1126B_VEPUCRU_BASE 0x80000 165b991d4b5SXuhui Lin #define RV1126B_NPUCRU_BASE 0x90000 166b991d4b5SXuhui Lin #define RV1126B_VDOCRU_BASE 0xA0000 167b991d4b5SXuhui Lin #define RV1126B_VCPCRU_BASE 0xB0000 1681be17b4cSElaine Zhang #define RV1126B_SBUSCRU_BASE 0x200000 169b991d4b5SXuhui Lin 170b991d4b5SXuhui Lin #define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE) 171b991d4b5SXuhui Lin #define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE) 172b991d4b5SXuhui Lin #define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE) 173b991d4b5SXuhui Lin #define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE) 174b991d4b5SXuhui Lin #define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE) 1751be17b4cSElaine Zhang #define RV1126B_SBUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SBUSCRU_BASE) 176b991d4b5SXuhui Lin 177b991d4b5SXuhui Lin enum { 178b991d4b5SXuhui Lin /* CRU_CLK_SEL10_CON */ 179b991d4b5SXuhui Lin CLK_AUDIO_FRAC1_SRC_SEL_SHIFT = 12, 180b991d4b5SXuhui Lin CLK_AUDIO_FRAC1_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC1_SRC_SEL_SHIFT, 181b991d4b5SXuhui Lin CLK_AUDIO_FRAC0_SRC_SEL_SHIFT = 10, 182b991d4b5SXuhui Lin CLK_AUDIO_FRAC0_SRC_SEL_MASK = 0x3 << CLK_AUDIO_FRAC0_SRC_SEL_SHIFT, 183b991d4b5SXuhui Lin CLK_UART_FRAC1_SRC_SEL_SHIFT = 8, 184b991d4b5SXuhui Lin CLK_UART_FRAC1_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC1_SRC_SEL_SHIFT, 185b991d4b5SXuhui Lin CLK_UART_FRAC0_SRC_SEL_SHIFT = 6, 186b991d4b5SXuhui Lin CLK_UART_FRAC0_SRC_SEL_MASK = 0x3 << CLK_UART_FRAC0_SRC_SEL_SHIFT, 187b991d4b5SXuhui Lin CLK_CM_FRAC2_SRC_SEL_SHIFT = 4, 188b991d4b5SXuhui Lin CLK_CM_FRAC2_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC2_SRC_SEL_SHIFT, 189b991d4b5SXuhui Lin CLK_CM_FRAC1_SRC_SEL_SHIFT = 2, 190b991d4b5SXuhui Lin CLK_CM_FRAC1_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC1_SRC_SEL_SHIFT, 191b991d4b5SXuhui Lin CLK_CM_FRAC0_SRC_SEL_SHIFT = 0, 192b991d4b5SXuhui Lin CLK_CM_FRAC0_SRC_SEL_MASK = 0x3 << CLK_CM_FRAC0_SRC_SEL_SHIFT, 193b991d4b5SXuhui Lin CLK_FRAC_SRC_SEL_24M = 0, 194b991d4b5SXuhui Lin CLK_FRAC_SRC_SEL_GPLL, 195b991d4b5SXuhui Lin CLK_FRAC_SRC_SEL_AUPLL, 196b991d4b5SXuhui Lin CLK_FRAC_SRC_SEL_CPLL, 197b991d4b5SXuhui Lin 198b991d4b5SXuhui Lin /* CRU_CLK_SEL12_CON */ 199b991d4b5SXuhui Lin SCLK_UART1_SEL_SHIFT = 13, 200b991d4b5SXuhui Lin SCLK_UART1_SEL_MASK = 0x7 << SCLK_UART1_SEL_SHIFT, 201b991d4b5SXuhui Lin SCLK_UART1_DIV_SHIFT = 8, 202b991d4b5SXuhui Lin SCLK_UART1_DIV_MASK = 0x1f << SCLK_UART1_DIV_SHIFT, 203b991d4b5SXuhui Lin SCLK_UART0_SRC_SEL_SHIFT = 5, 204b991d4b5SXuhui Lin SCLK_UART0_SRC_SEL_MASK = 0x7 << SCLK_UART0_SRC_SEL_SHIFT, 205b991d4b5SXuhui Lin SCLK_UART_SEL_OSC = 0, 206b991d4b5SXuhui Lin SCLK_UART_SEL_CM_FRAC0, 207b991d4b5SXuhui Lin SCLK_UART_SEL_CM_FRAC1, 208b991d4b5SXuhui Lin SCLK_UART_SEL_CM_FRAC2, 209b991d4b5SXuhui Lin SCLK_UART_SEL_UART_FRAC0, 210b991d4b5SXuhui Lin SCLK_UART_SEL_UART_FRAC1, 211b991d4b5SXuhui Lin SCLK_UART0_SRC_DIV_SHIFT = 0, 212b991d4b5SXuhui Lin SCLK_UART0_SRC_DIV_MASK = 0x1f << SCLK_UART0_SRC_DIV_SHIFT, 213b991d4b5SXuhui Lin 214b991d4b5SXuhui Lin /* CRU_CLK_SEL13_CON */ 215b991d4b5SXuhui Lin SCLK_UART3_SEL_SHIFT = 13, 216b991d4b5SXuhui Lin SCLK_UART3_SEL_MASK = 0x7 << SCLK_UART3_SEL_SHIFT, 217b991d4b5SXuhui Lin SCLK_UART3_DIV_SHIFT = 8, 218b991d4b5SXuhui Lin SCLK_UART3_DIV_MASK = 0x1f << SCLK_UART3_DIV_SHIFT, 219b991d4b5SXuhui Lin SCLK_UART2_SEL_SHIFT = 5, 220b991d4b5SXuhui Lin SCLK_UART2_SEL_MASK = 0x7 << SCLK_UART2_SEL_SHIFT, 221b991d4b5SXuhui Lin SCLK_UART2_DIV_SHIFT = 0, 222b991d4b5SXuhui Lin SCLK_UART2_DIV_MASK = 0x1f << SCLK_UART2_DIV_SHIFT, 223b991d4b5SXuhui Lin 224b991d4b5SXuhui Lin /* CRU_CLK_SEL14_CON */ 225b991d4b5SXuhui Lin SCLK_UART5_SEL_SHIFT = 13, 226b991d4b5SXuhui Lin SCLK_UART5_SEL_MASK = 0x7 << SCLK_UART5_SEL_SHIFT, 227b991d4b5SXuhui Lin SCLK_UART5_DIV_SHIFT = 8, 228b991d4b5SXuhui Lin SCLK_UART5_DIV_MASK = 0x1f << SCLK_UART5_DIV_SHIFT, 229b991d4b5SXuhui Lin SCLK_UART4_SEL_SHIFT = 5, 230b991d4b5SXuhui Lin SCLK_UART4_SEL_MASK = 0x7 << SCLK_UART4_SEL_SHIFT, 231b991d4b5SXuhui Lin SCLK_UART4_DIV_SHIFT = 0, 232b991d4b5SXuhui Lin SCLK_UART4_DIV_MASK = 0x1f << SCLK_UART4_DIV_SHIFT, 233b991d4b5SXuhui Lin 234b991d4b5SXuhui Lin /* CRU_CLK_SEL15_CON */ 235b991d4b5SXuhui Lin SCLK_UART7_SEL_SHIFT = 13, 236b991d4b5SXuhui Lin SCLK_UART7_SEL_MASK = 0x7 << SCLK_UART7_SEL_SHIFT, 237b991d4b5SXuhui Lin SCLK_UART7_DIV_SHIFT = 8, 238b991d4b5SXuhui Lin SCLK_UART7_DIV_MASK = 0x1f << SCLK_UART7_DIV_SHIFT, 239b991d4b5SXuhui Lin SCLK_UART6_SEL_SHIFT = 5, 240b991d4b5SXuhui Lin SCLK_UART6_SEL_MASK = 0x7 << SCLK_UART6_SEL_SHIFT, 241b991d4b5SXuhui Lin SCLK_UART6_DIV_SHIFT = 0, 242b991d4b5SXuhui Lin SCLK_UART6_DIV_MASK = 0x1f << SCLK_UART6_DIV_SHIFT, 243b991d4b5SXuhui Lin 244b991d4b5SXuhui Lin /* CRU_CLK_SEL25_CON */ 245b991d4b5SXuhui Lin CLK_FRAC_NUMERATOR_SHIFT = 16, 246b991d4b5SXuhui Lin CLK_FRAC_NUMERATOR_MASK = 0xffff << 16, 247b991d4b5SXuhui Lin CLK_FRAC_DENOMINATOR_SHIFT = 0, 248b991d4b5SXuhui Lin CLK_FRAC_DENOMINATOR_MASK = 0xffff, 249b991d4b5SXuhui Lin CLK_FRAC_H_NUMERATOR_SHIFT = 8, 250b991d4b5SXuhui Lin CLK_FRAC_H_NUMERATOR_MASK = 0xff << 8, 251b991d4b5SXuhui Lin CLK_FRAC_H_DENOMINATOR_SHIFT = 0, 252b991d4b5SXuhui Lin CLK_FRAC_H_DENOMINATOR_MASK = 0xff, 253b991d4b5SXuhui Lin 254d744c1e3SElaine Zhang /* CRU_CLK_SEL43_CON */ 255d744c1e3SElaine Zhang DCLK_VOP_SEL_SHIFT = 8, 256d744c1e3SElaine Zhang DCLK_VOP_SEL_MASK = 0x1 << DCLK_VOP_SEL_SHIFT, 257d744c1e3SElaine Zhang DCLK_VOP_SEL_GPLL = 0, 258d744c1e3SElaine Zhang DCLK_VOP_SEL_CPLL, 259d744c1e3SElaine Zhang DCLK_VOP_DIV_SHIFT = 0, 260d744c1e3SElaine Zhang DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT, 261d744c1e3SElaine Zhang 262b991d4b5SXuhui Lin /* CRU_CLK_SEL44_CON */ 263b991d4b5SXuhui Lin HCLK_BUS_SEL_SHIFT = 10, 264b991d4b5SXuhui Lin HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT, 265b991d4b5SXuhui Lin HCLK_BUS_SEL_200M = 0, 266b991d4b5SXuhui Lin HCLK_BUS_SEL_100M, 267b991d4b5SXuhui Lin ACLK_BUS_SEL_SHIFT = 8, 268b991d4b5SXuhui Lin ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT, 269b991d4b5SXuhui Lin ACLK_BUS_SEL_400M = 0, 270b991d4b5SXuhui Lin ACLK_BUS_SEL_300M, 271b991d4b5SXuhui Lin ACLK_BUS_SEL_200M, 272b991d4b5SXuhui Lin ACLK_TOP_SEL_SHIFT = 6, 273b991d4b5SXuhui Lin ACLK_TOP_SEL_MASK = 0x3 << ACLK_TOP_SEL_SHIFT, 274b991d4b5SXuhui Lin ACLK_TOP_SEL_600M = 0, 275b991d4b5SXuhui Lin ACLK_TOP_SEL_400M, 276b991d4b5SXuhui Lin ACLK_TOP_SEL_200M, 277b991d4b5SXuhui Lin 278b991d4b5SXuhui Lin /* CRU_CLK_SEL45_CON */ 279*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_DIV_SHIFT = 11, 280*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_DIV_MASK = 0x1f << CLK_GMAC_PTP_REF_SRC_DIV_SHIFT, 281*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_SEL_SHIFT = 10, 282*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_SEL_MASK = 0x1 << CLK_GMAC_PTP_REF_SRC_SEL_SHIFT, 283*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_SEL_CPLL = 0, 284*56591f59SElaine Zhang CLK_GMAC_PTP_REF_SRC_SEL_24M, 285b991d4b5SXuhui Lin CLK_SDMMC_SEL_SHIFT = 8, 286b991d4b5SXuhui Lin CLK_SDMMC_SEL_MASK = 0x3 << CLK_SDMMC_SEL_SHIFT, 287b991d4b5SXuhui Lin CLK_SDMMC_SEL_GPLL = 0, 288b991d4b5SXuhui Lin CLK_SDMMC_SEL_CPLL, 289b991d4b5SXuhui Lin CLK_SDMMC_SEL_24M, 290b991d4b5SXuhui Lin CLK_SDMMC_DIV_SHIFT = 0, 291b991d4b5SXuhui Lin CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT, 292b991d4b5SXuhui Lin 293b991d4b5SXuhui Lin /* CRU_CLK_SEL46_CON */ 294b991d4b5SXuhui Lin TCLK_WDT_HPMCU_SEL_SHIFT = 14, 295b991d4b5SXuhui Lin TCLK_WDT_HPMCU_SEL_MASK = 0x1 << TCLK_WDT_HPMCU_SEL_SHIFT, 296b991d4b5SXuhui Lin TCLK_WDT_S_SEL_SHIFT = 13, 297b991d4b5SXuhui Lin TCLK_WDT_S_SEL_MASK = 0x1 << TCLK_WDT_S_SEL_SHIFT, 298b991d4b5SXuhui Lin TCLK_WDT_NS_SEL_SHIFT = 12, 299b991d4b5SXuhui Lin TCLK_WDT_NS_SEL_MASK = 0x1 << TCLK_WDT_NS_SEL_SHIFT, 300b991d4b5SXuhui Lin TCLK_WDT_SEL_100M = 0, 301b991d4b5SXuhui Lin TCLK_WDT_SEL_OSC, 302b991d4b5SXuhui Lin 303b991d4b5SXuhui Lin /* CRU_CLK_SEL47_CON */ 304b991d4b5SXuhui Lin ACLK_PERI_SEL_SHIFT = 13, 305b991d4b5SXuhui Lin ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT, 306b991d4b5SXuhui Lin ACLK_PERI_SEL_200M = 0, 307b991d4b5SXuhui Lin ACLK_PERI_SEL_24M, 308b991d4b5SXuhui Lin PCLK_PERI_SEL_SHIFT = 12, 309b991d4b5SXuhui Lin PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT, 310b991d4b5SXuhui Lin PCLK_PERI_SEL_100M = 0, 311b991d4b5SXuhui Lin PCLK_PERI_SEL_24M, 312b991d4b5SXuhui Lin 313b991d4b5SXuhui Lin /* CRU_CLK_SEL50_CON */ 314b991d4b5SXuhui Lin ACLK_RKCE_SEL_SHIFT = 13, 315b991d4b5SXuhui Lin ACLK_RKCE_SEL_MASK = 0x1 << ACLK_RKCE_SEL_SHIFT, 316b991d4b5SXuhui Lin ACLK_RKCE_SEL_200M = 0, 317b991d4b5SXuhui Lin ACLK_RKCE_SEL_24M, 318b991d4b5SXuhui Lin CLK_PKA_RKCE_SEL_SHIFT = 12, 319b991d4b5SXuhui Lin CLK_PKA_RKCE_SEL_MASK = 0x1 << CLK_PKA_RKCE_SEL_SHIFT, 320b991d4b5SXuhui Lin CLK_PKA_RKCE_SEL_300M = 0, 321b991d4b5SXuhui Lin CLK_PKA_RKCE_SEL_200M, 322b991d4b5SXuhui Lin CLK_PWM3_SEL_SHIFT = 11, 323b991d4b5SXuhui Lin CLK_PWM3_SEL_MASK = 0x1 << CLK_PWM3_SEL_SHIFT, 324b991d4b5SXuhui Lin CLK_PWM2_SEL_SHIFT = 10, 325b991d4b5SXuhui Lin CLK_PWM2_SEL_MASK = 0x1 << CLK_PWM2_SEL_SHIFT, 326b991d4b5SXuhui Lin CLK_PWM0_SEL_SHIFT = 8, 327b991d4b5SXuhui Lin CLK_PWM0_SEL_MASK = 0x1 << CLK_PWM0_SEL_SHIFT, 328b991d4b5SXuhui Lin CLK_PWM_SEL_100M = 0, 329b991d4b5SXuhui Lin CLK_PWM_SEL_24M, 330b991d4b5SXuhui Lin CLK_SPI1_SEL_SHIFT = 4, 331b991d4b5SXuhui Lin CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 332b991d4b5SXuhui Lin CLK_SPI0_SEL_SHIFT = 2, 333b991d4b5SXuhui Lin CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 334b991d4b5SXuhui Lin CLK_SPI0_SEL_200M = 0, 335b991d4b5SXuhui Lin CLK_SPI0_SEL_100M, 336b991d4b5SXuhui Lin CLK_SPI0_SEL_50M, 337b991d4b5SXuhui Lin CLK_SPI0_SEL_24M, 338b991d4b5SXuhui Lin CLK_I2C_SEL_SHIFT = 1, 339b991d4b5SXuhui Lin CLK_I2C_SEL_MASK = 0x1 << CLK_I2C_SEL_SHIFT, 340b991d4b5SXuhui Lin CLK_I2C_SEL_200M = 0, 341b991d4b5SXuhui Lin CLK_I2C_SEL_24M, 342b991d4b5SXuhui Lin 343b991d4b5SXuhui Lin /* CRU_CLK_SEL63_CON */ 344b991d4b5SXuhui Lin CLK_SARADC2_SEL_SHIFT = 14, 345b991d4b5SXuhui Lin CLK_SARADC2_SEL_MASK = 0x1 << CLK_SARADC2_SEL_SHIFT, 346b991d4b5SXuhui Lin CLK_SARADC1_SEL_SHIFT = 13, 347b991d4b5SXuhui Lin CLK_SARADC1_SEL_MASK = 0x1 << CLK_SARADC1_SEL_SHIFT, 348b991d4b5SXuhui Lin CLK_SARADC0_SEL_SHIFT = 12, 349b991d4b5SXuhui Lin CLK_SARADC0_SEL_MASK = 0x1 << CLK_SARADC0_SEL_SHIFT, 350b991d4b5SXuhui Lin CLK_SARADC_SEL_200M = 0, 351b991d4b5SXuhui Lin CLK_SARADC_SEL_24M, 352b991d4b5SXuhui Lin CLK_SARADC2_DIV_SHIFT = 8, 353b991d4b5SXuhui Lin CLK_SARADC2_DIV_MASK = 0x7 << CLK_SARADC2_DIV_SHIFT, 354b991d4b5SXuhui Lin CLK_SARADC1_DIV_SHIFT = 4, 355b991d4b5SXuhui Lin CLK_SARADC1_DIV_MASK = 0x7 << CLK_SARADC1_DIV_SHIFT, 356b991d4b5SXuhui Lin CLK_SARADC0_DIV_SHIFT = 0, 357b991d4b5SXuhui Lin CLK_SARADC0_DIV_MASK = 0x7 << CLK_SARADC0_DIV_SHIFT, 358b991d4b5SXuhui Lin 359*56591f59SElaine Zhang /* CRU_CLK_SEL69_CON */ 360*56591f59SElaine Zhang CLK_MAC_OUT2IO_DIV_SHIFT = 8, 361*56591f59SElaine Zhang CLK_MAC_OUT2IO_DIV_MASK = 0x7f << CLK_MAC_OUT2IO_DIV_SHIFT, 362*56591f59SElaine Zhang CLK_MAC_OUT2IO_SEL_SHIFT = 6, 363*56591f59SElaine Zhang CLK_MAC_OUT2IO_SEL_MASK = 0x3 << CLK_MAC_OUT2IO_SEL_SHIFT, 364*56591f59SElaine Zhang CLK_MAC_OUT2IO_SEL_GPLL = 0, 365*56591f59SElaine Zhang CLK_MAC_OUT2IO_SEL_CPLL, 366*56591f59SElaine Zhang CLK_MAC_OUT2IO_SEL_24M, 367*56591f59SElaine Zhang 368b991d4b5SXuhui Lin /* PMUCRU_CLK_SEL2_CON */ 369b991d4b5SXuhui Lin CLK_I2C2_SEL_SHIFT = 14, 370b991d4b5SXuhui Lin CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 371b991d4b5SXuhui Lin CLK_I2C2_SEL_24M = 0, 372b991d4b5SXuhui Lin CLK_I2C2_SEL_RCOSC, 373b991d4b5SXuhui Lin CLK_I2C2_SEL_100M, 374b991d4b5SXuhui Lin CLK_PWM1_SEL_SHIFT = 8, 375b991d4b5SXuhui Lin CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 376b991d4b5SXuhui Lin CLK_PWM1_SEL_24M = 0, 377b991d4b5SXuhui Lin CLK_PWM1_SEL_RCOSC, 378b991d4b5SXuhui Lin CLK_PWM1_SEL_100M, 379b991d4b5SXuhui Lin CLK_PWM1_DIV_SHIFT = 6, 380b991d4b5SXuhui Lin CLK_PWM1_DIV_MASK = 0x3 << CLK_PWM1_DIV_SHIFT, 381b991d4b5SXuhui Lin 382b991d4b5SXuhui Lin /* PMUCRU_CLK_SEL3_CON */ 383b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_SHIFT = 6, 384b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_MASK = 0x3 << TCLK_WDT_LPMCU_SEL_SHIFT, 385b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_OSC = 0, 386b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_RCOSC, 387b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_100M, 388b991d4b5SXuhui Lin TCLK_WDT_LPMCU_SEL_32K, 389b991d4b5SXuhui Lin SCLK_UART0_SEL_SHIFT = 0, 390b991d4b5SXuhui Lin SCLK_UART0_SEL_MASK = 0x3 << SCLK_UART0_SEL_SHIFT, 391b991d4b5SXuhui Lin SCLK_UART0_SEL_UART0_SRC = 0, 392b991d4b5SXuhui Lin SCLK_UART0_SEL_OSC, 393b991d4b5SXuhui Lin SCLK_UART0_SEL_RCOSC, 394b991d4b5SXuhui Lin 395b991d4b5SXuhui Lin /* PMU1CRU_CLK_SEL0_CON */ 396b991d4b5SXuhui Lin SCLK_1X_FSPI1_DIV_SHIFT = 2, 397b991d4b5SXuhui Lin SCLK_1X_FSPI1_DIV_MASK = 0x7 << SCLK_1X_FSPI1_DIV_SHIFT, 398b991d4b5SXuhui Lin SCLK_1X_FSPI1_SEL_SHIFT = 0, 399b991d4b5SXuhui Lin SCLK_1X_FSPI1_SEL_MASK = 0x3 << SCLK_1X_FSPI1_SEL_SHIFT, 400b991d4b5SXuhui Lin SCLK_1X_FSPI1_SEL_24M = 0, 401b991d4b5SXuhui Lin SCLK_1X_FSPI1_SEL_RCOSC, 402b991d4b5SXuhui Lin SCLK_1X_FSPI1_SEL_100M, 403b991d4b5SXuhui Lin }; 404b991d4b5SXuhui Lin #endif 405