141793000SKever Yang /* 241793000SKever Yang * (C) Copyright 2016 Rockchip Electronics Co., Ltd 341793000SKever Yang * 441793000SKever Yang * SPDX-License-Identifier: GPL-2.0+ 541793000SKever Yang */ 641793000SKever Yang 741793000SKever Yang #ifndef __ASM_ARCH_CRU_RK3328_H_ 841793000SKever Yang #define __ASM_ARCH_CRU_RK3328_H_ 941793000SKever Yang 1041793000SKever Yang #include <common.h> 1141793000SKever Yang 1241793000SKever Yang struct rk3328_clk_priv { 1341793000SKever Yang struct rk3328_cru *cru; 1441793000SKever Yang ulong rate; 150b7db90fSElaine Zhang ulong cpll_hz; 160b7db90fSElaine Zhang ulong gpll_hz; 17f7913bc1SElaine Zhang ulong armclk_hz; 18f7913bc1SElaine Zhang ulong armclk_enter_hz; 19f7913bc1SElaine Zhang ulong armclk_init_hz; 20f7913bc1SElaine Zhang bool sync_kernel; 21f7913bc1SElaine Zhang bool set_armclk_rate; 2241793000SKever Yang }; 2341793000SKever Yang 2441793000SKever Yang struct rk3328_cru { 2541793000SKever Yang u32 apll_con[5]; 2641793000SKever Yang u32 reserved1[3]; 2741793000SKever Yang u32 dpll_con[5]; 2841793000SKever Yang u32 reserved2[3]; 2941793000SKever Yang u32 cpll_con[5]; 3041793000SKever Yang u32 reserved3[3]; 3141793000SKever Yang u32 gpll_con[5]; 3241793000SKever Yang u32 reserved4[3]; 3341793000SKever Yang u32 mode_con; 3441793000SKever Yang u32 misc; 3541793000SKever Yang u32 reserved5[2]; 3641793000SKever Yang u32 glb_cnt_th; 3741793000SKever Yang u32 glb_rst_st; 3841793000SKever Yang u32 glb_srst_snd_value; 3941793000SKever Yang u32 glb_srst_fst_value; 4041793000SKever Yang u32 npll_con[5]; 4141793000SKever Yang u32 reserved6[(0x100 - 0xb4) / 4]; 4241793000SKever Yang u32 clksel_con[53]; 4341793000SKever Yang u32 reserved7[(0x200 - 0x1d4) / 4]; 4441793000SKever Yang u32 clkgate_con[29]; 4541793000SKever Yang u32 reserved8[3]; 4641793000SKever Yang u32 ssgtbl[32]; 4741793000SKever Yang u32 softrst_con[12]; 4841793000SKever Yang u32 reserved9[(0x380 - 0x330) / 4]; 4941793000SKever Yang u32 sdmmc_con[2]; 5041793000SKever Yang u32 sdio_con[2]; 5141793000SKever Yang u32 emmc_con[2]; 5241793000SKever Yang u32 sdmmc_ext_con[2]; 5341793000SKever Yang }; 5441793000SKever Yang check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); 550b7db90fSElaine Zhang 560b7db90fSElaine Zhang /* PX30 pll id */ 570b7db90fSElaine Zhang enum rk3328_pll_id { 580b7db90fSElaine Zhang APLL, 590b7db90fSElaine Zhang DPLL, 600b7db90fSElaine Zhang CPLL, 610b7db90fSElaine Zhang GPLL, 620b7db90fSElaine Zhang NPLL, 630b7db90fSElaine Zhang PLL_COUNT, 640b7db90fSElaine Zhang }; 650b7db90fSElaine Zhang 660b7db90fSElaine Zhang struct rk3328_clk_info { 670b7db90fSElaine Zhang unsigned long id; 680b7db90fSElaine Zhang char *name; 690b7db90fSElaine Zhang bool is_cru; 700b7db90fSElaine Zhang }; 710b7db90fSElaine Zhang 720b7db90fSElaine Zhang #define MHz 1000 * 1000 7341793000SKever Yang #define OSC_HZ (24 * MHz) 7441793000SKever Yang #define APLL_HZ (600 * MHz) 750b7db90fSElaine Zhang #define GPLL_HZ 491520000 760b7db90fSElaine Zhang #define CPLL_HZ (1200 * MHz) 770b7db90fSElaine Zhang #define ACLK_BUS_HZ (150 * MHz) 780b7db90fSElaine Zhang #define ACLK_PERI_HZ (150 * MHz) 7941793000SKever Yang #define PWM_CLOCK_HZ (74 * MHz) 8041793000SKever Yang 810b7db90fSElaine Zhang #define RK3328_PLL_CON(x) ((x) * 0x4) 820b7db90fSElaine Zhang #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100) 830b7db90fSElaine Zhang #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200) 840b7db90fSElaine Zhang #define RK3328_MODE_CON 0x80 850b7db90fSElaine Zhang 860b7db90fSElaine Zhang enum { 870b7db90fSElaine Zhang /* CLKSEL_CON0 */ 880b7db90fSElaine Zhang CLK_BUS_PLL_SEL_CPLL = 0, 890b7db90fSElaine Zhang CLK_BUS_PLL_SEL_GPLL = 1, 900b7db90fSElaine Zhang CLK_BUS_PLL_SEL_SHIFT = 13, 910b7db90fSElaine Zhang CLK_BUS_PLL_SEL_MASK = 3 << CLK_BUS_PLL_SEL_SHIFT, 920b7db90fSElaine Zhang ACLK_BUS_DIV_CON_SHIFT = 8, 930b7db90fSElaine Zhang ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT, 940b7db90fSElaine Zhang CORE_CLK_PLL_SEL_SHIFT = 6, 950b7db90fSElaine Zhang CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT, 960b7db90fSElaine Zhang CORE_CLK_PLL_SEL_APLL = 0, 970b7db90fSElaine Zhang CORE_CLK_PLL_SEL_GPLL, 980b7db90fSElaine Zhang CORE_CLK_PLL_SEL_NPLL = 3, 990b7db90fSElaine Zhang CORE_DIV_CON_SHIFT = 0, 1000b7db90fSElaine Zhang CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, 1010b7db90fSElaine Zhang 1020b7db90fSElaine Zhang /* CLKSEL_CON1 */ 1030b7db90fSElaine Zhang PCLK_BUS_DIV_CON_SHIFT = 12, 1040b7db90fSElaine Zhang PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT, 1050b7db90fSElaine Zhang HCLK_BUS_DIV_CON_SHIFT = 8, 1060b7db90fSElaine Zhang HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT, 1070b7db90fSElaine Zhang CORE_ACLK_DIV_SHIFT = 4, 1080b7db90fSElaine Zhang CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT, 1090b7db90fSElaine Zhang CORE_DBG_DIV_SHIFT = 0, 1100b7db90fSElaine Zhang CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT, 1110b7db90fSElaine Zhang 112*67a2a1ddSDavid Wu /* CLKSEL_CON26 */ 113*67a2a1ddSDavid Wu GMAC2PHY_PLL_SEL_SHIFT = 7, 114*67a2a1ddSDavid Wu GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT, 115*67a2a1ddSDavid Wu GMAC2PHY_PLL_SEL_CPLL = 0, 116*67a2a1ddSDavid Wu GMAC2PHY_PLL_SEL_GPLL = 1, 117*67a2a1ddSDavid Wu GMAC2PHY_CLK_DIV_MASK = 0x1f, 118*67a2a1ddSDavid Wu GMAC2PHY_CLK_DIV_SHIFT = 0, 119*67a2a1ddSDavid Wu 1200b7db90fSElaine Zhang /* CLKSEL_CON27 */ 1210b7db90fSElaine Zhang GMAC2IO_PLL_SEL_SHIFT = 7, 1220b7db90fSElaine Zhang GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, 1230b7db90fSElaine Zhang GMAC2IO_PLL_SEL_CPLL = 0, 1240b7db90fSElaine Zhang GMAC2IO_PLL_SEL_GPLL = 1, 1250b7db90fSElaine Zhang GMAC2IO_CLK_DIV_MASK = 0x1f, 1260b7db90fSElaine Zhang GMAC2IO_CLK_DIV_SHIFT = 0, 1270b7db90fSElaine Zhang 1280b7db90fSElaine Zhang /* CLKSEL_CON28 */ 1290b7db90fSElaine Zhang CLK_PERI_PLL_SEL_CPLL = 0, 1300b7db90fSElaine Zhang CLK_PERI_PLL_SEL_GPLL, 1310b7db90fSElaine Zhang CLK_PERI_PLL_SEL_HDMIPHY, 1320b7db90fSElaine Zhang CLK_PERI_PLL_SEL_SHIFT = 6, 1330b7db90fSElaine Zhang CLK_PERI_PLL_SEL_MASK = 3 << CLK_PERI_PLL_SEL_SHIFT, 1340b7db90fSElaine Zhang ACLK_PERI_DIV_CON_SHIFT = 0, 1350b7db90fSElaine Zhang ACLK_PERI_DIV_CON_MASK = 0x1f, 1360b7db90fSElaine Zhang 1370b7db90fSElaine Zhang /* CLKSEL_CON29 */ 1380b7db90fSElaine Zhang PCLK_PERI_DIV_CON_SHIFT = 4, 1390b7db90fSElaine Zhang PCLK_PERI_DIV_CON_MASK = 0x7 << PCLK_PERI_DIV_CON_SHIFT, 1400b7db90fSElaine Zhang HCLK_PERI_DIV_CON_SHIFT = 0, 1410b7db90fSElaine Zhang HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT, 1420b7db90fSElaine Zhang 143cf04b7e8SElaine Zhang /* CLKSEL_CON20 */ 144cf04b7e8SElaine Zhang CRYPTO_PLL_SEL_SHIFT = 7, 145cf04b7e8SElaine Zhang CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT, 146cf04b7e8SElaine Zhang CRYPTO_PLL_SEL_CPLL = 0, 147cf04b7e8SElaine Zhang CRYPTO_PLL_SEL_GPLL, 148cf04b7e8SElaine Zhang CRYPTO_DIV_SHIFT = 0, 149cf04b7e8SElaine Zhang CRYPTO_DIV_MASK = 0x7f << CRYPTO_DIV_SHIFT, 150cf04b7e8SElaine Zhang 1510b7db90fSElaine Zhang /* CLKSEL_CON22 */ 1520b7db90fSElaine Zhang CLK_TSADC_DIV_CON_SHIFT = 0, 1530b7db90fSElaine Zhang CLK_TSADC_DIV_CON_MASK = 0x3ff, 1540b7db90fSElaine Zhang 1550b7db90fSElaine Zhang /* CLKSEL_CON23 */ 1560b7db90fSElaine Zhang CLK_SARADC_DIV_CON_SHIFT = 0, 1570b7db90fSElaine Zhang CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), 1580b7db90fSElaine Zhang CLK_SARADC_DIV_CON_WIDTH = 10, 1590b7db90fSElaine Zhang 1600b7db90fSElaine Zhang /* CLKSEL_CON24 */ 1610b7db90fSElaine Zhang CLK_PWM_PLL_SEL_CPLL = 0, 1620b7db90fSElaine Zhang CLK_PWM_PLL_SEL_GPLL, 1630b7db90fSElaine Zhang CLK_PWM_PLL_SEL_SHIFT = 15, 1640b7db90fSElaine Zhang CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT, 1650b7db90fSElaine Zhang CLK_PWM_DIV_CON_SHIFT = 8, 1660b7db90fSElaine Zhang CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT, 1670b7db90fSElaine Zhang 1680b7db90fSElaine Zhang CLK_SPI_PLL_SEL_CPLL = 0, 1690b7db90fSElaine Zhang CLK_SPI_PLL_SEL_GPLL, 1700b7db90fSElaine Zhang CLK_SPI_PLL_SEL_SHIFT = 7, 1710b7db90fSElaine Zhang CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT, 1720b7db90fSElaine Zhang CLK_SPI_DIV_CON_SHIFT = 0, 1730b7db90fSElaine Zhang CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT, 1740b7db90fSElaine Zhang 1750b7db90fSElaine Zhang /* CLKSEL_CON30 */ 1760b7db90fSElaine Zhang CLK_SDMMC_PLL_SEL_CPLL = 0, 1770b7db90fSElaine Zhang CLK_SDMMC_PLL_SEL_GPLL, 1780b7db90fSElaine Zhang CLK_SDMMC_PLL_SEL_24M, 1790b7db90fSElaine Zhang CLK_SDMMC_PLL_SEL_USBPHY, 1800b7db90fSElaine Zhang CLK_SDMMC_PLL_SHIFT = 8, 1810b7db90fSElaine Zhang CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT, 1820b7db90fSElaine Zhang CLK_SDMMC_DIV_CON_SHIFT = 0, 1830b7db90fSElaine Zhang CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT, 1840b7db90fSElaine Zhang 1850b7db90fSElaine Zhang /* CLKSEL_CON32 */ 1860b7db90fSElaine Zhang CLK_EMMC_PLL_SEL_CPLL = 0, 1870b7db90fSElaine Zhang CLK_EMMC_PLL_SEL_GPLL, 1880b7db90fSElaine Zhang CLK_EMMC_PLL_SEL_24M, 1890b7db90fSElaine Zhang CLK_EMMC_PLL_SEL_USBPHY, 1900b7db90fSElaine Zhang CLK_EMMC_PLL_SHIFT = 8, 1910b7db90fSElaine Zhang CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT, 1920b7db90fSElaine Zhang CLK_EMMC_DIV_CON_SHIFT = 0, 1930b7db90fSElaine Zhang CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT, 1940b7db90fSElaine Zhang 1950b7db90fSElaine Zhang /* CLKSEL_CON34 */ 1960b7db90fSElaine Zhang CLK_I2C_PLL_SEL_CPLL = 0, 1970b7db90fSElaine Zhang CLK_I2C_PLL_SEL_GPLL, 1980b7db90fSElaine Zhang CLK_I2C_DIV_CON_MASK = 0x7f, 1990b7db90fSElaine Zhang CLK_I2C_PLL_SEL_MASK = 1, 2000b7db90fSElaine Zhang CLK_I2C1_PLL_SEL_SHIFT = 15, 2010b7db90fSElaine Zhang CLK_I2C1_DIV_CON_SHIFT = 8, 2020b7db90fSElaine Zhang CLK_I2C0_PLL_SEL_SHIFT = 7, 2030b7db90fSElaine Zhang CLK_I2C0_DIV_CON_SHIFT = 0, 2040b7db90fSElaine Zhang 2050b7db90fSElaine Zhang /* CLKSEL_CON35 */ 2060b7db90fSElaine Zhang CLK_I2C3_PLL_SEL_SHIFT = 15, 2070b7db90fSElaine Zhang CLK_I2C3_DIV_CON_SHIFT = 8, 2080b7db90fSElaine Zhang CLK_I2C2_PLL_SEL_SHIFT = 7, 2090b7db90fSElaine Zhang CLK_I2C2_DIV_CON_SHIFT = 0, 2100b7db90fSElaine Zhang 2110b7db90fSElaine Zhang /* CRU_CLK_SEL37_CON */ 2120b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_CPLL = 0, 2130b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_GPLL = 1, 2140b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_HDMIPHY = 2, 2150b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_USB480M = 3, 2160b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_SHIFT = 6, 2170b7db90fSElaine Zhang ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT, 2180b7db90fSElaine Zhang ACLK_VIO_DIV_CON_SHIFT = 0, 2190b7db90fSElaine Zhang ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT, 2200b7db90fSElaine Zhang HCLK_VIO_DIV_CON_SHIFT = 8, 2210b7db90fSElaine Zhang HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT, 2220b7db90fSElaine Zhang 2230b7db90fSElaine Zhang /* CRU_CLK_SEL39_CON */ 2240b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_CPLL = 0, 2250b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_GPLL = 1, 2260b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_HDMIPHY = 2, 2270b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_USB480M = 3, 2280b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_SHIFT = 6, 2290b7db90fSElaine Zhang ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT, 2300b7db90fSElaine Zhang ACLK_VOP_DIV_CON_SHIFT = 0, 2310b7db90fSElaine Zhang ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 2320b7db90fSElaine Zhang 2330b7db90fSElaine Zhang /* CRU_CLK_SEL40_CON */ 2340b7db90fSElaine Zhang DCLK_LCDC_PLL_SEL_GPLL = 0, 2350b7db90fSElaine Zhang DCLK_LCDC_PLL_SEL_CPLL = 1, 2360b7db90fSElaine Zhang DCLK_LCDC_PLL_SEL_SHIFT = 0, 2370b7db90fSElaine Zhang DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT, 2380b7db90fSElaine Zhang DCLK_LCDC_SEL_HDMIPHY = 0, 2390b7db90fSElaine Zhang DCLK_LCDC_SEL_PLL = 1, 2400b7db90fSElaine Zhang DCLK_LCDC_SEL_SHIFT = 1, 2410b7db90fSElaine Zhang DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT, 2420b7db90fSElaine Zhang DCLK_LCDC_DIV_CON_SHIFT = 8, 2430b7db90fSElaine Zhang DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT, 24441793000SKever Yang }; 24541793000SKever Yang 24641793000SKever Yang #endif /* __ASM_ARCH_CRU_RK3328_H_ */ 247