1c6f7c1a3SJoseph Chen /* SPDX-License-Identifier: GPL-2.0 */ 2c6f7c1a3SJoseph Chen /* 3c6f7c1a3SJoseph Chen * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4c6f7c1a3SJoseph Chen * Author: Joseph Chen <chenjh@rock-chips.com> 5c6f7c1a3SJoseph Chen */ 6c6f7c1a3SJoseph Chen 7c6f7c1a3SJoseph Chen #ifndef _ASM_ARCH_CRU_RK3528_H 8c6f7c1a3SJoseph Chen #define _ASM_ARCH_CRU_RK3528_H 9c6f7c1a3SJoseph Chen 10c6f7c1a3SJoseph Chen #define MHz 1000000 11c6f7c1a3SJoseph Chen #define KHz 1000 12c6f7c1a3SJoseph Chen #define OSC_HZ (24 * MHz) 13c6f7c1a3SJoseph Chen 14161d3423SJoseph Chen #define CPU_PVTPLL_HZ (1200 * MHz) 15161d3423SJoseph Chen #define APLL_HZ (600 * MHz) 16c6f7c1a3SJoseph Chen #define GPLL_HZ (1188 * MHz) 17c6f7c1a3SJoseph Chen #define CPLL_HZ (996 * MHz) 18c6f7c1a3SJoseph Chen #define PPLL_HZ (1000 * MHz) 19c6f7c1a3SJoseph Chen 20c6f7c1a3SJoseph Chen /* RK3528 pll id */ 21c6f7c1a3SJoseph Chen enum rk3528_pll_id { 22c6f7c1a3SJoseph Chen APLL, 23c6f7c1a3SJoseph Chen CPLL, 24c6f7c1a3SJoseph Chen GPLL, 25c6f7c1a3SJoseph Chen PPLL, 26c6f7c1a3SJoseph Chen DPLL, 27c6f7c1a3SJoseph Chen PLL_COUNT, 28c6f7c1a3SJoseph Chen }; 29c6f7c1a3SJoseph Chen 30c6f7c1a3SJoseph Chen struct rk3528_clk_info { 31c6f7c1a3SJoseph Chen unsigned long id; 32c6f7c1a3SJoseph Chen char *name; 33c6f7c1a3SJoseph Chen }; 34c6f7c1a3SJoseph Chen 35c6f7c1a3SJoseph Chen struct rk3528_clk_priv { 36c6f7c1a3SJoseph Chen struct rk3528_cru *cru; 37c6f7c1a3SJoseph Chen struct rk3528_sysgrf *grf; 38c6f7c1a3SJoseph Chen ulong ppll_hz; 39c6f7c1a3SJoseph Chen ulong gpll_hz; 40c6f7c1a3SJoseph Chen ulong cpll_hz; 41c6f7c1a3SJoseph Chen ulong armclk_hz; 42c6f7c1a3SJoseph Chen ulong armclk_enter_hz; 43c6f7c1a3SJoseph Chen ulong armclk_init_hz; 44c6f7c1a3SJoseph Chen bool sync_kernel; 45c6f7c1a3SJoseph Chen bool set_armclk_rate; 46c6f7c1a3SJoseph Chen }; 47c6f7c1a3SJoseph Chen 48c6f7c1a3SJoseph Chen struct rk3528_pll { 49c6f7c1a3SJoseph Chen unsigned int con0; 50c6f7c1a3SJoseph Chen unsigned int con1; 51c6f7c1a3SJoseph Chen unsigned int con2; 52c6f7c1a3SJoseph Chen unsigned int con3; 53c6f7c1a3SJoseph Chen unsigned int con4; 54c6f7c1a3SJoseph Chen unsigned int reserved0[3]; 55c6f7c1a3SJoseph Chen }; 56c6f7c1a3SJoseph Chen 57c6f7c1a3SJoseph Chen struct rk3528_cru { 58c6f7c1a3SJoseph Chen uint32_t apll_con[5]; 59c6f7c1a3SJoseph Chen uint32_t reserved0014[3]; 60c6f7c1a3SJoseph Chen uint32_t cpll_con[5]; 61c6f7c1a3SJoseph Chen uint32_t reserved0034[11]; 62c6f7c1a3SJoseph Chen uint32_t gpll_con[5]; 63c6f7c1a3SJoseph Chen uint32_t reserved0074[51+32]; 64c6f7c1a3SJoseph Chen uint32_t reserved01c0[48]; 65c6f7c1a3SJoseph Chen uint32_t mode_con[1]; 66c6f7c1a3SJoseph Chen uint32_t reserved0284[31]; 67c6f7c1a3SJoseph Chen uint32_t clksel_con[91]; 68c6f7c1a3SJoseph Chen uint32_t reserved046c[229]; 69c6f7c1a3SJoseph Chen uint32_t gate_con[46]; 70c6f7c1a3SJoseph Chen uint32_t reserved08b8[82]; 71c6f7c1a3SJoseph Chen uint32_t softrst_con[47]; 72c6f7c1a3SJoseph Chen uint32_t reserved0abc[81]; 73c6f7c1a3SJoseph Chen uint32_t glb_cnt_th; 74c6f7c1a3SJoseph Chen uint32_t glb_rst_st; 75c6f7c1a3SJoseph Chen uint32_t glb_srst_fst; 76c6f7c1a3SJoseph Chen uint32_t glb_srst_snd; 77c6f7c1a3SJoseph Chen uint32_t glb_rst_con; 78c6f7c1a3SJoseph Chen uint32_t reserved0c14[6]; 79c6f7c1a3SJoseph Chen uint32_t corewfi_con; 80c6f7c1a3SJoseph Chen uint32_t reserved0c30[15604]; 81c6f7c1a3SJoseph Chen 82c6f7c1a3SJoseph Chen /* pmucru */ 83c6f7c1a3SJoseph Chen uint32_t reserved10000[192]; 84c6f7c1a3SJoseph Chen uint32_t pmuclksel_con[3]; 85c6f7c1a3SJoseph Chen uint32_t reserved1030c[317]; 86c6f7c1a3SJoseph Chen uint32_t pmugate_con[3]; 87c6f7c1a3SJoseph Chen uint32_t reserved1080c[125]; 88c6f7c1a3SJoseph Chen uint32_t pmusoftrst_con[3]; 89c6f7c1a3SJoseph Chen uint32_t reserved10a08[7550+8191]; 90c6f7c1a3SJoseph Chen 91c6f7c1a3SJoseph Chen /* pciecru */ 92c6f7c1a3SJoseph Chen uint32_t reserved20000[32]; 93c6f7c1a3SJoseph Chen uint32_t ppll_con[5]; 94c6f7c1a3SJoseph Chen uint32_t reserved20094[155]; 95c6f7c1a3SJoseph Chen uint32_t pcieclksel_con[2]; 96c6f7c1a3SJoseph Chen uint32_t reserved20308[318]; 97c6f7c1a3SJoseph Chen uint32_t pciegate_con; 98c6f7c1a3SJoseph Chen }; 99c6f7c1a3SJoseph Chen check_member(rk3528_cru, pciegate_con, 0x20800); 100c6f7c1a3SJoseph Chen 101c6f7c1a3SJoseph Chen struct rk3528_grf_clk_priv { 102c6f7c1a3SJoseph Chen struct rk3528_grf *grf; 103c6f7c1a3SJoseph Chen }; 104c6f7c1a3SJoseph Chen 105c6f7c1a3SJoseph Chen struct pll_rate_table { 106c6f7c1a3SJoseph Chen unsigned long rate; 107c6f7c1a3SJoseph Chen unsigned int fbdiv; 108c6f7c1a3SJoseph Chen unsigned int postdiv1; 109c6f7c1a3SJoseph Chen unsigned int refdiv; 110c6f7c1a3SJoseph Chen unsigned int postdiv2; 111c6f7c1a3SJoseph Chen unsigned int dsmpd; 112c6f7c1a3SJoseph Chen unsigned int frac; 113c6f7c1a3SJoseph Chen }; 114c6f7c1a3SJoseph Chen 115c6f7c1a3SJoseph Chen #define RK3528_PMU_CRU_BASE 0x10000 116c6f7c1a3SJoseph Chen #define RK3528_PCIE_CRU_BASE 0x20000 117c6f7c1a3SJoseph Chen #define RK3528_DDRPHY_CRU_BASE 0x28000 118c6f7c1a3SJoseph Chen #define RK3528_PLL_CON(x) ((x) * 0x4) 119c6f7c1a3SJoseph Chen #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) 120c6f7c1a3SJoseph Chen #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) 121c6f7c1a3SJoseph Chen #define RK3528_MODE_CON 0x280 122c6f7c1a3SJoseph Chen #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) 123c6f7c1a3SJoseph Chen #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) 124c6f7c1a3SJoseph Chen #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) 125c6f7c1a3SJoseph Chen #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) 126c6f7c1a3SJoseph Chen 127c6f7c1a3SJoseph Chen #define RK3528_DIV_ACLK_M_CORE_SHIFT 11 128*b5328075SFinley Xiao #define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT) 129c6f7c1a3SJoseph Chen #define RK3528_DIV_PCLK_DBG_SHIFT 1 130*b5328075SFinley Xiao #define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT) 131c6f7c1a3SJoseph Chen 132c6f7c1a3SJoseph Chen enum { 133e855752aSJoseph Chen /* CRU_CLKSEL_CON00 */ 134e855752aSJoseph Chen CLK_MATRIX_50M_SRC_DIV_SHIFT = 2, 135e855752aSJoseph Chen CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT, 136e855752aSJoseph Chen CLK_MATRIX_100M_SRC_DIV_SHIFT = 7, 137e855752aSJoseph Chen CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT, 138c6f7c1a3SJoseph Chen 139e855752aSJoseph Chen /* CRU_CLKSEL_CON01 */ 140e855752aSJoseph Chen CLK_MATRIX_150M_SRC_DIV_SHIFT = 0, 141e855752aSJoseph Chen CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT, 142e855752aSJoseph Chen CLK_MATRIX_200M_SRC_DIV_SHIFT = 5, 143e855752aSJoseph Chen CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT, 144e855752aSJoseph Chen CLK_MATRIX_250M_SRC_DIV_SHIFT = 10, 145e855752aSJoseph Chen CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT, 146e855752aSJoseph Chen CLK_MATRIX_250M_SRC_SEL_SHIFT = 15, 147e855752aSJoseph Chen CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT, 148c6f7c1a3SJoseph Chen 149e855752aSJoseph Chen /* CRU_CLKSEL_CON02 */ 150e855752aSJoseph Chen CLK_MATRIX_300M_SRC_DIV_SHIFT = 0, 151e855752aSJoseph Chen CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT, 152e855752aSJoseph Chen CLK_MATRIX_339M_SRC_DIV_SHIFT = 5, 153e855752aSJoseph Chen CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT, 154e855752aSJoseph Chen CLK_MATRIX_400M_SRC_DIV_SHIFT = 10, 155e855752aSJoseph Chen CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT, 156c6f7c1a3SJoseph Chen 157e855752aSJoseph Chen /* CRU_CLKSEL_CON03 */ 158e855752aSJoseph Chen CLK_MATRIX_500M_SRC_DIV_SHIFT = 6, 159e855752aSJoseph Chen CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT, 160e855752aSJoseph Chen CLK_MATRIX_500M_SRC_SEL_SHIFT = 11, 161e855752aSJoseph Chen CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT, 162c6f7c1a3SJoseph Chen 163e855752aSJoseph Chen /* CRU_CLKSEL_CON04 */ 164e855752aSJoseph Chen CLK_MATRIX_600M_SRC_DIV_SHIFT = 0, 165e855752aSJoseph Chen CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT, 166e855752aSJoseph Chen CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U, 167e855752aSJoseph Chen CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U, 168e855752aSJoseph Chen CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U, 169e855752aSJoseph Chen CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U, 170c6f7c1a3SJoseph Chen 171e855752aSJoseph Chen /* PMUCRU_CLKSEL_CON00 */ 172e855752aSJoseph Chen CLK_I2C2_SEL_SHIFT = 0, 173e855752aSJoseph Chen CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT, 174c6f7c1a3SJoseph Chen 175e855752aSJoseph Chen /* PCIE_CRU_CLKSEL_CON01 */ 176e855752aSJoseph Chen PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7, 177e855752aSJoseph Chen PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT, 178e855752aSJoseph Chen PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11, 179e855752aSJoseph Chen PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT, 180c6f7c1a3SJoseph Chen 181e855752aSJoseph Chen /* CRU_CLKSEL_CON32 */ 182e855752aSJoseph Chen DCLK_VOP_SRC0_SEL_SHIFT = 10, 183e855752aSJoseph Chen DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT, 184e855752aSJoseph Chen DCLK_VOP_SRC0_DIV_SHIFT = 2, 185e855752aSJoseph Chen DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT, 186c6f7c1a3SJoseph Chen 187e855752aSJoseph Chen /* CRU_CLKSEL_CON33 */ 188e855752aSJoseph Chen DCLK_VOP_SRC1_SEL_SHIFT = 8, 189e855752aSJoseph Chen DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT, 190e855752aSJoseph Chen DCLK_VOP_SRC1_DIV_SHIFT = 0, 191e855752aSJoseph Chen DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT, 192c6f7c1a3SJoseph Chen 193e855752aSJoseph Chen /* CRU_CLKSEL_CON43 */ 194e855752aSJoseph Chen CLK_CORE_CRYPTO_SEL_SHIFT = 14, 195e855752aSJoseph Chen CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 196e855752aSJoseph Chen ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U, 197e855752aSJoseph Chen ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT, 198c6f7c1a3SJoseph Chen 199e855752aSJoseph Chen /* CRU_CLKSEL_CON44 */ 200e855752aSJoseph Chen CLK_PWM0_SEL_SHIFT = 6, 201e855752aSJoseph Chen CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT, 202e855752aSJoseph Chen CLK_PWM1_SEL_SHIFT = 8, 203e855752aSJoseph Chen CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT, 204c6f7c1a3SJoseph Chen CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U, 205c6f7c1a3SJoseph Chen CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U, 206c6f7c1a3SJoseph Chen CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U, 207c6f7c1a3SJoseph Chen CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U, 208c6f7c1a3SJoseph Chen CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U, 209c6f7c1a3SJoseph Chen CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U, 210e855752aSJoseph Chen CLK_PKA_CRYPTO_SEL_SHIFT = 0, 211e855752aSJoseph Chen CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 212c6f7c1a3SJoseph Chen CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 213c6f7c1a3SJoseph Chen CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 214c6f7c1a3SJoseph Chen CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 215c6f7c1a3SJoseph Chen CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 216c6f7c1a3SJoseph Chen CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U, 217c6f7c1a3SJoseph Chen CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U, 218c6f7c1a3SJoseph Chen CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U, 219c6f7c1a3SJoseph Chen CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U, 220c6f7c1a3SJoseph Chen 221e855752aSJoseph Chen /* CRU_CLKSEL_CON60 */ 222e855752aSJoseph Chen CLK_MATRIX_25M_SRC_DIV_SHIFT = 2, 223e855752aSJoseph Chen CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT, 224e855752aSJoseph Chen CLK_MATRIX_125M_SRC_DIV_SHIFT = 10, 225e855752aSJoseph Chen CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT, 226c6f7c1a3SJoseph Chen 227e855752aSJoseph Chen /* CRU_CLKSEL_CON61 */ 228e855752aSJoseph Chen SCLK_SFC_DIV_SHIFT = 6, 229e855752aSJoseph Chen SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT, 230e855752aSJoseph Chen SCLK_SFC_SEL_SHIFT = 12, 231e855752aSJoseph Chen SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, 232c6f7c1a3SJoseph Chen SCLK_SFC_SEL_CLK_GPLL_MUX = 0U, 233c6f7c1a3SJoseph Chen SCLK_SFC_SEL_CLK_CPLL_MUX = 1U, 234c6f7c1a3SJoseph Chen SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U, 235c6f7c1a3SJoseph Chen 236e855752aSJoseph Chen /* CRU_CLKSEL_CON62 */ 237e855752aSJoseph Chen CCLK_SRC_EMMC_DIV_SHIFT = 0, 238e855752aSJoseph Chen CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT, 239e855752aSJoseph Chen CCLK_SRC_EMMC_SEL_SHIFT = 6, 240e855752aSJoseph Chen CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT, 241e855752aSJoseph Chen BCLK_EMMC_SEL_SHIFT = 8, 242e855752aSJoseph Chen BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT, 243c6f7c1a3SJoseph Chen 244e855752aSJoseph Chen /* CRU_CLKSEL_CON63 */ 245e855752aSJoseph Chen CLK_I2C3_SEL_SHIFT = 12, 246e855752aSJoseph Chen CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT, 247e855752aSJoseph Chen CLK_I2C5_SEL_SHIFT = 14, 248e855752aSJoseph Chen CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT, 249e855752aSJoseph Chen CLK_SPI1_SEL_SHIFT = 10, 250e855752aSJoseph Chen CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 251c6f7c1a3SJoseph Chen 252e855752aSJoseph Chen /* CRU_CLKSEL_CON64 */ 253e855752aSJoseph Chen CLK_I2C6_SEL_SHIFT = 0, 254e855752aSJoseph Chen CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT, 255e855752aSJoseph Chen 256e855752aSJoseph Chen /* CRU_CLKSEL_CON74 */ 257e855752aSJoseph Chen CLK_SARADC_DIV_SHIFT = 0, 258e855752aSJoseph Chen CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT, 259e855752aSJoseph Chen CLK_TSADC_DIV_SHIFT = 3, 260e855752aSJoseph Chen CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT, 261e855752aSJoseph Chen CLK_TSADC_TSEN_DIV_SHIFT = 8, 262e855752aSJoseph Chen CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT, 263e855752aSJoseph Chen 264e855752aSJoseph Chen /* CRU_CLKSEL_CON79 */ 265e855752aSJoseph Chen CLK_I2C1_SEL_SHIFT = 9, 266e855752aSJoseph Chen CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT, 267e855752aSJoseph Chen CLK_I2C0_SEL_SHIFT = 11, 268e855752aSJoseph Chen CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT, 269e855752aSJoseph Chen CLK_SPI0_SEL_SHIFT = 13, 270e855752aSJoseph Chen CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT, 271e855752aSJoseph Chen 272e855752aSJoseph Chen /* CRU_CLKSEL_CON83 */ 273e855752aSJoseph Chen ACLK_VOP_ROOT_DIV_SHIFT = 12, 274e855752aSJoseph Chen ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT, 275e855752aSJoseph Chen ACLK_VOP_ROOT_SEL_SHIFT = 15, 276e855752aSJoseph Chen ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT, 277e855752aSJoseph Chen 278e855752aSJoseph Chen /* CRU_CLKSEL_CON84 */ 279e855752aSJoseph Chen DCLK_VOP0_SEL_SHIFT = 0, 280e855752aSJoseph Chen DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT, 281e855752aSJoseph Chen DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U, 282e855752aSJoseph Chen DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U, 283e855752aSJoseph Chen ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U, 284e855752aSJoseph Chen ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U, 285e855752aSJoseph Chen DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U, 286e855752aSJoseph Chen DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U, 287e855752aSJoseph Chen 288e855752aSJoseph Chen /* CRU_CLKSEL_CON85 */ 289e855752aSJoseph Chen CLK_I2C4_SEL_SHIFT = 13, 290e855752aSJoseph Chen CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT, 291e855752aSJoseph Chen CLK_I2C7_SEL_SHIFT = 0, 292e855752aSJoseph Chen CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT, 293e855752aSJoseph Chen CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U, 294e855752aSJoseph Chen CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U, 295e855752aSJoseph Chen CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U, 296e855752aSJoseph Chen CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U, 297e855752aSJoseph Chen CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U, 298e855752aSJoseph Chen CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U, 299e855752aSJoseph Chen CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U, 300e855752aSJoseph Chen CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U, 301e855752aSJoseph Chen CCLK_SRC_SDMMC0_DIV_SHIFT = 0, 302e855752aSJoseph Chen CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT, 303e855752aSJoseph Chen CCLK_SRC_SDMMC0_SEL_SHIFT = 6, 304e855752aSJoseph Chen CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT, 305c6f7c1a3SJoseph Chen CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U, 306c6f7c1a3SJoseph Chen CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U, 307c6f7c1a3SJoseph Chen CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U, 308c6f7c1a3SJoseph Chen BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U, 309c6f7c1a3SJoseph Chen BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U, 310c6f7c1a3SJoseph Chen BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U, 311c6f7c1a3SJoseph Chen BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U, 312c6f7c1a3SJoseph Chen CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U, 313c6f7c1a3SJoseph Chen CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U, 314c6f7c1a3SJoseph Chen CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U, 315c6f7c1a3SJoseph Chen 316e855752aSJoseph Chen /* CRU_CLKSEL_CON04 */ 317e855752aSJoseph Chen CLK_UART0_SRC_DIV_SHIFT = 5, 318e855752aSJoseph Chen CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT, 319e855752aSJoseph Chen /* CRU_CLKSEL_CON05 */ 320e855752aSJoseph Chen CLK_UART0_FRAC_DIV_SHIFT = 0, 321e855752aSJoseph Chen CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT, 322e855752aSJoseph Chen /* CRU_CLKSEL_CON06 */ 323e855752aSJoseph Chen SCLK_UART0_SRC_SEL_SHIFT = 0, 324e855752aSJoseph Chen SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT, 325e855752aSJoseph Chen CLK_UART1_SRC_DIV_SHIFT = 2, 326e855752aSJoseph Chen CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT, 327e855752aSJoseph Chen /* CRU_CLKSEL_CON07 */ 328e855752aSJoseph Chen CLK_UART1_FRAC_DIV_SHIFT = 0, 329e855752aSJoseph Chen CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT, 330e855752aSJoseph Chen /* CRU_CLKSEL_CON08 */ 331e855752aSJoseph Chen SCLK_UART1_SRC_SEL_SHIFT = 0, 332e855752aSJoseph Chen SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT, 333e855752aSJoseph Chen CLK_UART2_SRC_DIV_SHIFT = 2, 334e855752aSJoseph Chen CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT, 335e855752aSJoseph Chen /* CRU_CLKSEL_CON09 */ 336e855752aSJoseph Chen CLK_UART2_FRAC_DIV_SHIFT = 0, 337e855752aSJoseph Chen CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT, 338e855752aSJoseph Chen /* CRU_CLKSEL_CON10 */ 339e855752aSJoseph Chen SCLK_UART2_SRC_SEL_SHIFT = 0, 340e855752aSJoseph Chen SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT, 341e855752aSJoseph Chen CLK_UART3_SRC_DIV_SHIFT = 2, 342e855752aSJoseph Chen CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT, 343e855752aSJoseph Chen /* CRU_CLKSEL_CON11 */ 344e855752aSJoseph Chen CLK_UART3_FRAC_DIV_SHIFT = 0, 345e855752aSJoseph Chen CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT, 346e855752aSJoseph Chen /* CRU_CLKSEL_CON12 */ 347e855752aSJoseph Chen SCLK_UART3_SRC_SEL_SHIFT = 0, 348e855752aSJoseph Chen SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT, 349e855752aSJoseph Chen CLK_UART4_SRC_DIV_SHIFT = 2, 350e855752aSJoseph Chen CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT, 351e855752aSJoseph Chen /* CRU_CLKSEL_CON13 */ 352e855752aSJoseph Chen CLK_UART4_FRAC_DIV_SHIFT = 0, 353e855752aSJoseph Chen CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT, 354e855752aSJoseph Chen /* CRU_CLKSEL_CON14 */ 355e855752aSJoseph Chen SCLK_UART4_SRC_SEL_SHIFT = 0, 356e855752aSJoseph Chen SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT, 357e855752aSJoseph Chen CLK_UART5_SRC_DIV_SHIFT = 2, 358e855752aSJoseph Chen CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT, 359e855752aSJoseph Chen /* CRU_CLKSEL_CON15 */ 360e855752aSJoseph Chen CLK_UART5_FRAC_DIV_SHIFT = 0, 361e855752aSJoseph Chen CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT, 362e855752aSJoseph Chen /* CRU_CLKSEL_CON16 */ 363e855752aSJoseph Chen SCLK_UART5_SRC_SEL_SHIFT = 0, 364e855752aSJoseph Chen SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT, 365e855752aSJoseph Chen CLK_UART6_SRC_DIV_SHIFT = 2, 366e855752aSJoseph Chen CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT, 367e855752aSJoseph Chen /* CRU_CLKSEL_CON17 */ 368e855752aSJoseph Chen CLK_UART6_FRAC_DIV_SHIFT = 0, 369e855752aSJoseph Chen CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT, 370e855752aSJoseph Chen /* CRU_CLKSEL_CON18 */ 371e855752aSJoseph Chen SCLK_UART6_SRC_SEL_SHIFT = 0, 372e855752aSJoseph Chen SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT, 373e855752aSJoseph Chen CLK_UART7_SRC_DIV_SHIFT = 2, 374e855752aSJoseph Chen CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT, 375e855752aSJoseph Chen /* CRU_CLKSEL_CON19 */ 376e855752aSJoseph Chen CLK_UART7_FRAC_DIV_SHIFT = 0, 377e855752aSJoseph Chen CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT, 378e855752aSJoseph Chen /* CRU_CLKSEL_CON20 */ 379e855752aSJoseph Chen SCLK_UART7_SRC_SEL_SHIFT = 0, 380e855752aSJoseph Chen SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT, 381c6f7c1a3SJoseph Chen SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U, 382c6f7c1a3SJoseph Chen SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U, 383c6f7c1a3SJoseph Chen SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U, 384c6f7c1a3SJoseph Chen 385e855752aSJoseph Chen /* CRU_CLKSEL_CON60 */ 386e855752aSJoseph Chen CLK_GMAC1_VPU_25M_DIV_SHIFT = 2, 387e855752aSJoseph Chen CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT, 388e855752aSJoseph Chen /* CRU_CLKSEL_CON66 */ 389e855752aSJoseph Chen CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0, 390e855752aSJoseph Chen CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT, 391e855752aSJoseph Chen /* CRU_CLKSEL_CON84 */ 392e855752aSJoseph Chen CLK_GMAC0_SRC_DIV_SHIFT = 3, 393e855752aSJoseph Chen CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT, 394c6f7c1a3SJoseph Chen }; 395c6f7c1a3SJoseph Chen 396c6f7c1a3SJoseph Chen #endif 397