| e6712cf5 | 23-Apr-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: bpmp: mark device "not present" on boot timeout
This patch updates the state machine to "not present" if the bpmp firmware is not found in the system during boot. The suspend handler also che
Tegra: bpmp: mark device "not present" on boot timeout
This patch updates the state machine to "not present" if the bpmp firmware is not found in the system during boot. The suspend handler also checks now if the interface exists, before updating the internal state machine.
Reported by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Change-Id: If8fd7f8e412bb603944555c24826855226e7f48c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| da0f4743 | 09-Apr-2018 |
kalyani chidambaram <kalyanic@nvidia.com> |
Tegra210: clear PMC_DPD registers on resume
This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw.
Change-Id: I7881ef0a5
Tegra210: clear PMC_DPD registers on resume
This patch clears the PMC's DPD registers on resuming from System Suspend, for all Tegra210 platforms that support the sc7entry-fw.
Change-Id: I7881ef0a5f609ed28b158bc2f4016abea3c7f305 Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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| 3ca3c27c | 27-Feb-2018 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: support for System Suspend using sc7entry-fw binary
This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no long
Tegra: support for System Suspend using sc7entry-fw binary
This patch adds support to enter System Suspend on Tegra210 platforms without the traditional BPMP firmware. The BPMP firmware will no longer be supported on Tegra210 platforms and its functionality will be divided across the CPU and sc7entry-fw.
The sc7entry-fw takes care of performing the hardware sequence required to enter System Suspend (SC7 power state) from the COP. The CPU is required to load this firmware to the internal RAM of the COP and start the sequence. The CPU also make sure that the COP is off after cold boot and is only powered on when we want to start the actual System Suspend sequence.
The previous bootloader loads the firmware to TZDRAM and passes its base and size as part of the boot parameters. The EL3 layer is supposed to sanitize the parameters before touching the firmware blob.
To assist the warmboot code with the PMIC discovery, EL3 is also supposed to program PMC's scratch register #210, with appropriate values. Without these settings the warmboot code wont be able to get the device out of System Suspend.
Change-Id: I5a7b868512dbfd6cfefd55acf3978a1fd7ebf1e2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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