1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <stddef.h> 11 #include <string.h> 12 13 #include <platform_def.h> 14 15 #include <arch.h> 16 #include <arch_helpers.h> 17 #include <bl31/bl31.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <cortex_a53.h> 21 #include <cortex_a57.h> 22 #include <denver.h> 23 #include <drivers/console.h> 24 #include <lib/mmio.h> 25 #include <lib/utils.h> 26 #include <lib/utils_def.h> 27 #include <plat/common/platform.h> 28 29 #include <memctrl.h> 30 #include <profiler.h> 31 #include <tegra_def.h> 32 #include <tegra_platform.h> 33 #include <tegra_private.h> 34 35 /* length of Trusty's input parameters (in bytes) */ 36 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 37 38 /******************************************************************************* 39 * Declarations of linker defined symbols which will help us find the layout 40 * of trusted SRAM 41 ******************************************************************************/ 42 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 43 44 extern uint64_t tegra_bl31_phys_base; 45 46 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 47 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 48 .tzdram_size = TZDRAM_SIZE 49 }; 50 #ifdef SPD_trusty 51 static aapcs64_params_t bl32_args; 52 #endif 53 54 /******************************************************************************* 55 * This variable holds the non-secure image entry address 56 ******************************************************************************/ 57 extern uint64_t ns_image_entrypoint; 58 59 /******************************************************************************* 60 * Return a pointer to the 'entry_point_info' structure of the next image for 61 * security state specified. BL33 corresponds to the non-secure image type 62 * while BL32 corresponds to the secure image type. 63 ******************************************************************************/ 64 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 65 { 66 entry_point_info_t *ep = NULL; 67 68 /* return BL32 entry point info if it is valid */ 69 if (type == NON_SECURE) { 70 ep = &bl33_image_ep_info; 71 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 72 ep = &bl32_image_ep_info; 73 } 74 75 return ep; 76 } 77 78 /******************************************************************************* 79 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 80 * passes this platform specific information. 81 ******************************************************************************/ 82 plat_params_from_bl2_t *bl31_get_plat_params(void) 83 { 84 return &plat_bl31_params_from_bl2; 85 } 86 87 /******************************************************************************* 88 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 89 * info. 90 ******************************************************************************/ 91 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 92 u_register_t arg2, u_register_t arg3) 93 { 94 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 95 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 96 int32_t ret; 97 98 /* 99 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 100 * there's no argument to relay from a previous bootloader. Platforms 101 * might use custom ways to get arguments. 102 */ 103 if (arg_from_bl2 == NULL) { 104 arg_from_bl2 = plat_get_bl31_params(); 105 } 106 if (plat_params == NULL) { 107 plat_params = plat_get_bl31_plat_params(); 108 } 109 110 /* 111 * Copy BL3-3, BL3-2 entry point information. 112 * They are stored in Secure RAM, in BL2's address space. 113 */ 114 assert(arg_from_bl2 != NULL); 115 assert(arg_from_bl2->bl33_ep_info != NULL); 116 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 117 118 if (arg_from_bl2->bl32_ep_info != NULL) { 119 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 120 #ifdef SPD_trusty 121 /* save BL32 boot parameters */ 122 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); 123 #endif 124 } 125 126 /* 127 * Parse platform specific parameters 128 */ 129 assert(plat_params != NULL); 130 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 131 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 132 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 133 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 134 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; 135 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; 136 137 /* 138 * It is very important that we run either from TZDRAM or TZSRAM base. 139 * Add an explicit check here. 140 */ 141 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 142 (TEGRA_TZRAM_BASE != BL31_BASE)) { 143 panic(); 144 } 145 146 /* 147 * Enable console for the platform 148 */ 149 plat_enable_console(plat_params->uart_id); 150 151 /* 152 * The previous bootloader passes the base address of the shared memory 153 * location to store the boot profiler logs. Sanity check the 154 * address and initialise the profiler library, if it looks ok. 155 */ 156 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 157 PROFILER_SIZE_BYTES); 158 if (ret == (int32_t)0) { 159 160 /* store the membase for the profiler lib */ 161 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 162 plat_params->boot_profiler_shmem_base; 163 164 /* initialise the profiler library */ 165 boot_profiler_init(plat_params->boot_profiler_shmem_base, 166 TEGRA_TMRUS_BASE); 167 } 168 169 /* 170 * Add timestamp for platform early setup entry. 171 */ 172 boot_profiler_add_record("[TF] early setup entry"); 173 174 /* 175 * Initialize delay timer 176 */ 177 tegra_delay_timer_init(); 178 179 /* Early platform setup for Tegra SoCs */ 180 plat_early_platform_setup(); 181 182 /* 183 * Do initial security configuration to allow DRAM/device access. 184 */ 185 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 186 (uint32_t)plat_bl31_params_from_bl2.tzdram_size); 187 188 #if RELOCATE_BL32_IMAGE 189 /* 190 * The previous bootloader might not have placed the BL32 image 191 * inside the TZDRAM. Platform handler to allow relocation of BL32 192 * image to TZDRAM memory. This behavior might change per platform. 193 */ 194 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info); 195 #endif 196 197 /* 198 * Add timestamp for platform early setup exit. 199 */ 200 boot_profiler_add_record("[TF] early setup exit"); 201 202 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 203 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 204 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 205 } 206 207 #ifdef SPD_trusty 208 void plat_trusty_set_boot_args(aapcs64_params_t *args) 209 { 210 /* 211 * arg0 = TZDRAM aperture available for BL32 212 * arg1 = BL32 boot params 213 * arg2 = EKS Blob Length 214 * arg3 = Boot Profiler Carveout Base 215 */ 216 args->arg0 = bl32_args.arg0; 217 args->arg1 = bl32_args.arg2; 218 219 /* update EKS size */ 220 args->arg2 = bl32_args.arg4; 221 222 /* Profiler Carveout Base */ 223 args->arg3 = bl32_args.arg5; 224 } 225 #endif 226 227 /******************************************************************************* 228 * Initialize the gic, configure the SCR. 229 ******************************************************************************/ 230 void bl31_platform_setup(void) 231 { 232 /* 233 * Add timestamp for platform setup entry. 234 */ 235 boot_profiler_add_record("[TF] plat setup entry"); 236 237 /* Initialize the gic cpu and distributor interfaces */ 238 plat_gic_setup(); 239 240 /* 241 * Setup secondary CPU POR infrastructure. 242 */ 243 plat_secondary_setup(); 244 245 /* 246 * Initial Memory Controller configuration. 247 */ 248 tegra_memctrl_setup(); 249 250 /* 251 * Late setup handler to allow platforms to performs additional 252 * functionality. 253 * This handler gets called with MMU enabled. 254 */ 255 plat_late_platform_setup(); 256 257 /* 258 * Add timestamp for platform setup exit. 259 */ 260 boot_profiler_add_record("[TF] plat setup exit"); 261 262 INFO("BL3-1: Tegra platform setup complete\n"); 263 } 264 265 /******************************************************************************* 266 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 267 ******************************************************************************/ 268 void bl31_plat_runtime_setup(void) 269 { 270 /* 271 * During cold boot, it is observed that the arbitration 272 * bit is set in the Memory controller leading to false 273 * error interrupts in the non-secure world. To avoid 274 * this, clean the interrupt status register before 275 * booting into the non-secure world 276 */ 277 tegra_memctrl_clear_pending_interrupts(); 278 279 /* 280 * During boot, USB3 and flash media (SDMMC/SATA) devices need 281 * access to IRAM. Because these clients connect to the MC and 282 * do not have a direct path to the IRAM, the MC implements AHB 283 * redirection during boot to allow path to IRAM. In this mode 284 * accesses to a programmed memory address aperture are directed 285 * to the AHB bus, allowing access to the IRAM. This mode must be 286 * disabled before we jump to the non-secure world. 287 */ 288 tegra_memctrl_disable_ahb_redirection(); 289 290 /* 291 * Add final timestamp before exiting BL31. 292 */ 293 boot_profiler_add_record("[TF] bl31 exit"); 294 boot_profiler_deinit(); 295 } 296 297 /******************************************************************************* 298 * Perform the very early platform specific architectural setup here. At the 299 * moment this only intializes the mmu in a quick and dirty way. 300 ******************************************************************************/ 301 void bl31_plat_arch_setup(void) 302 { 303 uint64_t rw_start = BL31_RW_START; 304 uint64_t rw_size = BL_END - BL31_RW_START; 305 uint64_t rodata_start = BL_RO_DATA_BASE; 306 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; 307 uint64_t code_base = BL_CODE_BASE; 308 uint64_t code_size = BL_CODE_END - BL_CODE_BASE; 309 const mmap_region_t *plat_mmio_map = NULL; 310 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 311 312 /* 313 * Add timestamp for arch setup entry. 314 */ 315 boot_profiler_add_record("[TF] arch setup entry"); 316 317 /* add MMIO space */ 318 plat_mmio_map = plat_get_mmio_map(); 319 if (plat_mmio_map != NULL) { 320 mmap_add(plat_mmio_map); 321 } else { 322 WARN("MMIO map not available\n"); 323 } 324 325 /* add memory regions */ 326 mmap_add_region(rw_start, rw_start, 327 rw_size, 328 MT_MEMORY | MT_RW | MT_SECURE); 329 mmap_add_region(rodata_start, rodata_start, 330 rodata_size, 331 MT_RO_DATA | MT_SECURE); 332 mmap_add_region(code_base, code_base, 333 code_size, 334 MT_CODE | MT_SECURE); 335 336 /* map TZDRAM used by BL31 as coherent memory */ 337 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 338 mmap_add_region(params_from_bl2->tzdram_base, 339 params_from_bl2->tzdram_base, 340 BL31_SIZE, 341 MT_DEVICE | MT_RW | MT_SECURE); 342 } 343 344 /* set up translation tables */ 345 init_xlat_tables(); 346 347 /* enable the MMU */ 348 enable_mmu_el3(0); 349 350 /* 351 * Add timestamp for arch setup exit. 352 */ 353 boot_profiler_add_record("[TF] arch setup exit"); 354 355 INFO("BL3-1: Tegra: MMU enabled\n"); 356 } 357 358 /******************************************************************************* 359 * Check if the given NS DRAM range is valid 360 ******************************************************************************/ 361 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 362 { 363 uint64_t end = base + size_in_bytes - U(1); 364 365 /* 366 * Sanity check the input values 367 */ 368 if ((base == 0U) || (size_in_bytes == 0U)) { 369 ERROR("NS address 0x%llx (%lld bytes) is invalid\n", 370 base, size_in_bytes); 371 return -EINVAL; 372 } 373 374 /* 375 * Check if the NS DRAM address is valid 376 */ 377 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 378 (end > TEGRA_DRAM_END)) { 379 380 ERROR("NS address 0x%llx is out-of-bounds!\n", base); 381 return -EFAULT; 382 } 383 384 /* 385 * TZDRAM aperture contains the BL31 and BL32 images, so we need 386 * to check if the NS DRAM range overlaps the TZDRAM aperture. 387 */ 388 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 389 ERROR("NS address 0x%llx overlaps TZDRAM!\n", base); 390 return -ENOTSUP; 391 } 392 393 /* valid NS address */ 394 return 0; 395 } 396