1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MEMCTRL_V2_H 8 #define MEMCTRL_V2_H 9 10 #include <tegra_def.h> 11 12 #ifndef __ASSEMBLER__ 13 14 #include <lib/mmio.h> 15 #include <stdint.h> 16 17 /******************************************************************************* 18 * Structure to hold the transaction override settings to use to override 19 * client inputs 20 ******************************************************************************/ 21 typedef struct mc_txn_override_cfg { 22 uint32_t offset; 23 uint8_t cgid_tag; 24 } mc_txn_override_cfg_t; 25 26 #define mc_make_txn_override_cfg(off, val) \ 27 { \ 28 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \ 29 .cgid_tag = MC_TXN_OVERRIDE_ ## val \ 30 } 31 32 /******************************************************************************* 33 * Structure to hold the Stream ID to use to override client inputs 34 ******************************************************************************/ 35 typedef struct mc_streamid_override_cfg { 36 uint32_t offset; 37 uint8_t stream_id; 38 } mc_streamid_override_cfg_t; 39 40 /******************************************************************************* 41 * Structure to hold the Stream ID Security Configuration settings 42 ******************************************************************************/ 43 typedef struct mc_streamid_security_cfg { 44 char *name; 45 uint32_t offset; 46 int override_enable; 47 int override_client_inputs; 48 int override_client_ns_flag; 49 } mc_streamid_security_cfg_t; 50 51 #define OVERRIDE_DISABLE 1U 52 #define OVERRIDE_ENABLE 0U 53 #define CLIENT_FLAG_SECURE 0U 54 #define CLIENT_FLAG_NON_SECURE 1U 55 #define CLIENT_INPUTS_OVERRIDE 1U 56 #define CLIENT_INPUTS_NO_OVERRIDE 0U 57 /******************************************************************************* 58 * StreamID to indicate no SMMU translations (requests to be steered on the 59 * SMMU bypass path) 60 ******************************************************************************/ 61 #define MC_STREAM_ID_MAX 0x7FU 62 63 /******************************************************************************* 64 * Memory Controller SMMU Bypass config register 65 ******************************************************************************/ 66 #define MC_SMMU_BYPASS_CONFIG 0x1820U 67 #define MC_SMMU_BYPASS_CTRL_MASK 0x3U 68 #define MC_SMMU_BYPASS_CTRL_SHIFT 0U 69 #define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT) 70 #define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT) 71 #define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT) 72 #define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT) 73 #define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31) 74 #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ 75 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) 76 77 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ 78 { \ 79 .name = # off, \ 80 .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \ 81 MC_STREAMID_OVERRIDE_CFG_ ## off), \ 82 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \ 83 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \ 84 .override_enable = OVERRIDE_ ## access \ 85 } 86 87 #include <assert.h> 88 89 typedef struct mc_regs { 90 uint32_t reg; 91 uint32_t val; 92 } mc_regs_t; 93 94 #define mc_make_sid_override_cfg(name) \ 95 { \ 96 .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \ 97 .val = 0x00000000U, \ 98 } 99 100 #define mc_make_sid_security_cfg(name) \ 101 { \ 102 .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \ 103 .val = 0x00000000U, \ 104 } 105 106 #define mc_smmu_bypass_cfg \ 107 { \ 108 .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \ 109 .val = 0x00000000U, \ 110 } 111 112 #define _START_OF_TABLE_ \ 113 { \ 114 .reg = 0xCAFE05C7U, \ 115 .val = 0x00000000U, \ 116 } 117 118 #define _END_OF_TABLE_ \ 119 { \ 120 .reg = 0xFFFFFFFFU, \ 121 .val = 0xFFFFFFFFU, \ 122 } 123 124 /******************************************************************************* 125 * Structure to hold Memory Controller's Configuration settings 126 ******************************************************************************/ 127 typedef struct tegra_mc_settings { 128 const uint32_t *streamid_override_cfg; 129 uint32_t num_streamid_override_cfgs; 130 const mc_streamid_security_cfg_t *streamid_security_cfg; 131 uint32_t num_streamid_security_cfgs; 132 const mc_txn_override_cfg_t *txn_override_cfg; 133 uint32_t num_txn_override_cfgs; 134 void (*reconfig_mss_clients)(void); 135 void (*set_txn_overrides)(void); 136 mc_regs_t* (*get_mc_system_suspend_ctx)(void); 137 } tegra_mc_settings_t; 138 139 static inline uint32_t tegra_mc_read_32(uint32_t off) 140 { 141 return mmio_read_32(TEGRA_MC_BASE + off); 142 } 143 144 static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 145 { 146 mmio_write_32(TEGRA_MC_BASE + off, val); 147 } 148 149 #if defined(TEGRA_MC_STREAMID_BASE) 150 static inline uint32_t tegra_mc_streamid_read_32(uint32_t off) 151 { 152 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off); 153 } 154 155 static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val) 156 { 157 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val); 158 assert(mmio_read_32(TEGRA_MC_STREAMID_BASE + off) == val); 159 } 160 #endif 161 162 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \ 163 ((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \ 164 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED) 165 166 #define mc_set_pcfifo_ordered_boot_so_mss(id, client) \ 167 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED 168 169 #define mc_set_tsa_passthrough(client) \ 170 { \ 171 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 172 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \ 173 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 174 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 175 } 176 177 #define mc_set_tsa_w_passthrough(client) \ 178 { \ 179 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \ 180 (TSA_CONFIG_STATIC0_CSW_RESET_W & \ 181 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 182 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 183 } 184 185 #define mc_set_tsa_r_passthrough(client) \ 186 { \ 187 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \ 188 (TSA_CONFIG_STATIC0_CSR_RESET_R & \ 189 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \ 190 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \ 191 } 192 193 #define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \ 194 { \ 195 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \ 196 MC_TXN_OVERRIDE_##normal_axi_id | \ 197 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \ 198 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \ 199 MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ 200 } 201 202 /******************************************************************************* 203 * Handler to read memory configuration settings 204 * 205 * Implemented by SoCs under tegra/soc/txxx 206 ******************************************************************************/ 207 tegra_mc_settings_t *tegra_get_mc_settings(void); 208 209 /******************************************************************************* 210 * Handler to save MC settings before "System Suspend" to TZDRAM 211 * 212 * Implemented by Tegra common memctrl_v2 driver under common/drivers/memctrl 213 ******************************************************************************/ 214 void tegra_mc_save_context(uint64_t mc_ctx_addr); 215 216 /******************************************************************************* 217 * Handler to program the scratch registers with TZDRAM settings for the 218 * resume firmware. 219 * 220 * Implemented by SoCs under tegra/soc/txxx 221 ******************************************************************************/ 222 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes); 223 224 #endif /* __ASSEMBLER__ */ 225 226 #endif /* MEMCTRL_V2_H */ 227