| b39d2896 | 27-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1283 from jeenu-arm/sdei-fixes
SDEI fixes |
| 5724481f | 16-Feb-2018 |
David Cunado <david.cunado@arm.com> |
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by usin
Update ULL() macro and instances of ull to comply with MISRA
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes.
This patch resolves this for the ULL() macro by using ULL suffix instead
of the ull suffix.
Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01
Signed-off-by: David Cunado <david.cunado@arm.com>
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| f2928f5b | 16-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
SDEI: Add prioritisation clarification
To make exception handling amongst Secure components, require that SDEI
exception priorities must be assigned the lowest among Secure
priorities. Clarify docum
SDEI: Add prioritisation clarification
To make exception handling amongst Secure components, require that SDEI
exception priorities must be assigned the lowest among Secure
priorities. Clarify documentation to this effect.
Change-Id: I92524b7b7e9b3fa06a10c86372bc3c4dd18c00ad
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 101d01e2 | 10-Jan-2018 |
Soby Mathew <soby.mathew@arm.com> |
BL1: Deprecate the `bl1_init_bl2_mem_layout()` API
The `bl1_init_bl2_mem_layout()` API is now deprecated. The default weak
implementation of `bl1_plat_handle_post_image_load()` calculates the
BL2 me
BL1: Deprecate the `bl1_init_bl2_mem_layout()` API
The `bl1_init_bl2_mem_layout()` API is now deprecated. The default weak
implementation of `bl1_plat_handle_post_image_load()` calculates the
BL2 memory layout and populates the same in x1(r1). This ensures
compatibility for the deprecated API.
Change-Id: Id44bdc1f572dc42ee6ceef4036b3a46803689315
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 566034fc | 08-Feb-2018 |
Soby Mathew <soby.mathew@arm.com> |
Add image_id to bl1_plat_handle_post/pre_image_load()
This patch adds an argument to bl1_plat_post/pre_image_load() APIs
to make it more future proof. The default implementation of
these are moved t
Add image_id to bl1_plat_handle_post/pre_image_load()
This patch adds an argument to bl1_plat_post/pre_image_load() APIs
to make it more future proof. The default implementation of
these are moved to `plat_bl1_common.c` file.
These APIs are now invoked appropriately in the FWU code path prior
to or post image loading by BL1 and are not restricted
to LOAD_IMAGE_V2.
The patch also reorganizes some common platform files. The previous
`plat_bl2_el3_common.c` and `platform_helpers_default.c` files are
merged into a new `plat_bl_common.c` file.
NOTE: The addition of an argument to the above mentioned platform APIs
is not expected to have a great impact because these APIs were only
recently added and are unlikely to be used.
Change-Id: I0519caaee0f774dd33638ff63a2e597ea178c453
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| 38d96de6 | 23-Feb-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Fix Foundation FVP instructions in User Guide
The Arm Trusted Firmware is built by default for ARMv8-A version 8.0.
However, the Foundation FVP runs by default in the highest version of
the architec
Fix Foundation FVP instructions in User Guide
The Arm Trusted Firmware is built by default for ARMv8-A version 8.0.
However, the Foundation FVP runs by default in the highest version of
the architecture it supports. This causes problems when trying to run
the Arm Trusted Firmware on it.
This patch adds a note to the User Guide about this problem.
Change-Id: I0220fe1a9c66c2292149ad4a7ffe5e27ba08ab28
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 15e59585 | 12-Feb-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1256 from jeenu-arm/tsp-ehf
TSP changes for EHF |
| fb750ee1 | 10-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
interrupt-framework-design.rst: Cosmetic changes
Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
| 6027796f | 11-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
TSPD: Require NS preemption along with EL3 exception handling
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how
Non-secure interrupt affects TSPs execution. When TSP is executing:
1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received
at the TSP's exception vector, and TSP voluntarily preempts itself.
2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a
trap to EL3, which preempts TSP execution.
When EL3 exception handling is in place (i.e.,
EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system
with GICv3, pending NS interrupts while TSP is executing will be
signalled as FIQ (which traps to EL3). This situation necessitates the
same treatment applied to case (2) above.
Therefore, when EL3 exception handling is in place, additionally
require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1.
Strictly speaking, this is not required on a system with GICv2, but the
same model is uniformly followed regardless, for simplicity.
Relevant documentation updated.
Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 26ea3908 | 10-Jan-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
Deprecate one EL3 interrupt routing model with EL3 exception handling
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1,
EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-se
Deprecate one EL3 interrupt routing model with EL3 exception handling
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1,
EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and
secure execution.
The interrupt management framework currently treats EL3 interrupt
routing as valid. For the above reason, this patch makes them invalid
when EL3_EXCEPTION_HANDLING is in effect.
Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 11f001cb | 01-Feb-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
bl1: add bl1_plat_handle_{pre,post}_image_load()
Just like bl2_, add pre/post image load handlers for BL1. No argument
is needed since BL2 is the only image loaded by BL1.
Signed-off-by: Masahiro
bl1: add bl1_plat_handle_{pre,post}_image_load()
Just like bl2_, add pre/post image load handlers for BL1. No argument
is needed since BL2 is the only image loaded by BL1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| ba68ef55 | 01-Feb-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
bl2: add bl2_plat_handle_pre_image_load()
There are cases where we need to manipulate image information before
the load. For example, for decompressing data, we cannot load the
compressed images to
bl2: add bl2_plat_handle_pre_image_load()
There are cases where we need to manipulate image information before
the load. For example, for decompressing data, we cannot load the
compressed images to their final destination. Instead, we need to
load them to the temporary buffer for the decompressor.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| aca8a490 | 29-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1246 from sandrine-bailleux-arm/topics/sb/fix-cnp-doc
Fix documentation for CnP bit |
| 7c0a843f | 29-Jan-2018 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Fix documentation for CnP bit
The CnP bit documentation in the Firmware Design Guide incorrectly
used the term "Page Entries" instead of "Processing Elements".
Fix that.
Change-Id: Ie44ee99c281b7b1
Fix documentation for CnP bit
The CnP bit documentation in the Firmware Design Guide incorrectly
used the term "Page Entries" instead of "Processing Elements".
Fix that.
Change-Id: Ie44ee99c281b7b1a9ad90fba2c7d109f12425507
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 1b9e79e8 | 29-Jan-2018 |
Andreas Färber <afaerber@suse.de> |
docs: hikey: Fix typo
The correct name of the manufacturer is LeMaker.
Signed-off-by: Andreas Färber <afaerber@suse.de> |
| f478253d | 25-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1232 from masahir0y/uniphier
uniphier: migrate to BL2-AT-EL3 |
| 040f1e69 | 24-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1193 from jwerner-chromium/JW_coreboot
New console API and coreboot support [v4] |
| 247fc043 | 19-Dec-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
uniphier: switch to BL2-AT-EL3 and remove BL1 support
UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is
uniphier: switch to BL2-AT-EL3 and remove BL1 support
UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is entered at EL1-S. Now, this platform is able to avoid this waste.
Enable the BL2_AT_EL3 option, and remove BL1.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 17cd67d2 | 18-Sep-2017 |
Julius Werner <jwerner@chromium.org> |
Add default crash console code to hook up to new console API
This patch expands the weak stubs for the plat_crash_console_xxx
functions in common platform code to use the new console API for crash
o
Add default crash console code to hook up to new console API
This patch expands the weak stubs for the plat_crash_console_xxx
functions in common platform code to use the new console API for crash
output. This should make crash console output "just work" for most cases
without the need for the platform to explicitly set up a crash console.
For cases where the normal console framework doesn't work (e.g. very
early crashes, before the platform can register any consoles), platforms
are still able to override the functions just like before.
This feature requires the MULTI_CONSOLE_API compile-time flag to work.
For builds which don't have it set, this patch has no practical effect.
Change-Id: I80dd161cb43f9db59a0bad2dae33c6560cfac584
Signed-off-by: Julius Werner <jwerner@chromium.org>
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| 0d3a27e7 | 19-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1200 from robertovargas-arm/bl2-el3
Add BL2_AT_EL3 build option |
| 4cd1769f | 20-Nov-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
bl2-el3: Add documentation for BL2 at EL3
Update firmware-design.rst, porting-guide.rst and user-guide.rst
with the information about BL2 at EL3. Firmware-design.rst is
also update to explain how to
bl2-el3: Add documentation for BL2 at EL3
Update firmware-design.rst, porting-guide.rst and user-guide.rst
with the information about BL2 at EL3. Firmware-design.rst is
also update to explain how to test this feauture with FVP.
Change-Id: I86d64bc64594e13eb041cea9cefa3f7f3fa745bd
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 4fd4a32f | 15-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1217 from robertovargas-arm/doc-plat_try_next_boot_source
Add documentation about plat_try_next_boot_source to bl1_platform_setup |
| 5f3c7ce4 | 12-Jan-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1197 from dp-arm/dp/amu
AMUv1 support |
| 59902b7c | 13-Dec-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
AMU: Add plat interface to select which group 1 counters to enable
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which
group 1 counters should be enabled. The maximum number of group
AMU: Add plat interface to select which group 1 counters to enable
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which
group 1 counters should be enabled. The maximum number of group 1
counters supported by AMUv1 is 16 so the mask can be at most 0xffff.
If the platform does not define this mask, no group 1 counters are
enabled.
A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by
generic code to allocate an array to save and restore the counters on
CPU suspend.
Change-Id: I6d135badf4846292de931a43bb563077f42bb47b
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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| f62ad322 | 30-Nov-2017 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Workaround for CVE-2017-5715 on Cortex A57 and A72
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling
and enabling the MMU. To achieve this without performing any branch
instruc
Workaround for CVE-2017-5715 on Cortex A57 and A72
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling
and enabling the MMU. To achieve this without performing any branch
instruction, a per-cpu vbar is installed which executes the workaround
and then branches off to the corresponding vector entry in the main
vector table. A side effect of this change is that the main vbar is
configured before any reset handling. This is to allow the per-cpu
reset function to override the vbar setting.
This workaround is enabled by default on the affected CPUs.
Change-Id: I97788d38463a5840a410e3cea85ed297a1678265
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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