docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse

docs(security): update CVE-2024-7881 affected CPU revisions

This patch updates the affected versions for the following CPUs -
Cortex-X3 [1], Cortex-X4 [2], Cortex-X925 [3], Neoverse-V2 [4],
Neoverse-V3 [5] and Neoverse-V3AE [6].
Errata IDs for reference in the respective SDENs

Cortex-X3 - 3692984
Cortex-X4 - 3692983
Cortex-X925 - 3692980
Neoverse-V2 - 3696445
Neoverse-V3/V3AE - 3696307

[1] https://developer.arm.com/documentation/SDEN-2055130/latest/
[2] https://developer.arm.com/documentation/SDEN-2432808/latest
[3] https://developer.arm.com/documentation/109180/latest/
[4] https://developer.arm.com/documentation/SDEN-2332927/latest
[5] https://developer.arm.com/documentation/SDEN-2891958/latest/
[6] https://developer.arm.com/documentation/SDEN-2615521/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iad109561a144169fd3805c179a4f8e3bfdd59a65

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docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash

docs(security): update CVE-2024-7881 affected CPUs list

This patch updates the affected CPUs list to include the following
CPUs - C1-Premium, C1-Pro and C1-Ultra.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia2cc39d0f91bab89a911e271cf83c788d71bb85c

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docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing thes

docs(security): add CVE-2024-5660 and CVE-2024-7881 reference links

Add missing hyperlink targets for CVE-2024-5660 and CVE-2024-7881 in
cpu-specific-build-macros.rst to allow cross-referencing these CVEs
from documentation.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia3c003d5c359f101f230fbd54845f61117456abb

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Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): wor

Merge changes from topic "xl/a725-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A725 erratum 3456106
fix(cpus): workaround for Cortex-A725 erratum 3711914
fix(cpus): workaround for Cortex-A725 erratum 2936490
fix(cpus): workaround for Cortex-A725 erratum 2874943

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Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): u

Merge changes from topic "ar/feat_uinj" into integration

* changes:
feat(cpufeat): add support for FEAT_UINJ
feat(cpufeat): enable mandatory Armv9.4–Armv9.6 features by default
fix(cpufeat): update feature names and comments
fix(cpufeat): simplify AArch32 feature disablement

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Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workar

Merge changes from topic "xl/a65-errata" into integration

* changes:
fix(cpus): workaround for Cortex-A65 erratum 1541130
fix(cpus): workaround for Cortex-A65 erratum 1227419
fix(cpus): workaround for Cortex-A65 erratum 1179935

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fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3456106

Cortex-A725 erratum 3456106 is a Cat B erratum that applies
to revisions r0p0, r0p1 and r0p2, it is still open.

This erratum can be avoided by having Speculation Barrier (SB)
instruction after the writes to the PSTATE.SSBS.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I10d1e8cb4da19ba4101a5617245ff75866707d25
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be

fix(cpus): workaround for Cortex-A65 erratum 1541130

Cortex-A65 erratum 1541130 is a Cat B erratum that applies
to r0p0, r1p0, r1p1, r1p2 revisions of the CPU and is still open.

This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I72498f60f8449193ed4b5b2a9e7a08530e786ec3
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by

fix(cpus): workaround for Cortex-A725 erratum 3711914

Cortex-A725 erratum 3711914 is a Cat B erratum that applies
to revisions r0p0 and r0p1 and it is fixed in r0p2.

This erratum can be avoided by inserting a DMB LD after each DSB ST instruction.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: If3b9d3a0f495b3a172d3e6e5ca7afa8c30aeb4ea
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting

fix(cpus): workaround for Cortex-A725 erratum 2936490

Cortex-A725 erratum 2936490 is a Cat B erratum that applies
to revisions in r0p0, and is fixed in r0p1.

This erratum can be avoided by setting CPUACTLR2_EL1[37] to 1.
Setting this bit is expected to have a negligible performance impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I9833f8831ba3735a94763791a65be11b95c00bdb
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be

fix(cpus): workaround for Cortex-A725 erratum 2874943

Cortex-A725 erratum 2874943 is a Cat B erratum that applies
to revision r0p0 when FEAT_SPE is enabled, it is fixed in r0p1.

This erratum can be avoided by setting bits[58:57] to 0b11 in CPUACTLR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2832921/latest/

Change-Id: I686bbde8756d52afee92097ec05b97138b550025
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_E

fix(cpus): workaround for Cortex-A65 erratum 1227419

Cortex-A65 erratum 1227419 is a Cat B erratum that applies
to r0p0, r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[51] to 1.
This bit disables the cross-thread sharing in instruction uTLB.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: I42371e7d53fce3a7e085bf0b348f080fa323fb51
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49]

fix(cpus): workaround for Cortex-A65 erratum 1179935

Cortex-A65 erratum 1179935 is a Cat B erratum that applies
to r0p0, it is fixed in r1p0.

This erratum can be avoided by setting CPUACTLR_EL1[49] to 1. The bit
prevents translation table walks from allocating lines into the
L1 cache. This has a negligible impact on performance when an
L2 cache is present.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1065159/latest/

Change-Id: Ie59a4897f849269a590d8fa2d25cceab5f2cba3c
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setti

fix(cpus): workaround for Cortex-A76AE erratum 2371140

Cortex-A76AE erratum 2371140 is a Cat B erratum that applies
to all revisions <= r1p1, and is still open.

This erratum can be avoided by setting CPUACTLR2_EL1[0] to 1. The
bit force PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches. There might be a small performance
degradation to this workaround for certain workloads that share data.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: Id65846bebde1a0911ba11956202d0d255d3c8c82
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a

fix(cpus): workaround for Cortex-A76AE erratum 1969401

Cortex-A76AE erratum 1969401 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by inserting a DMB ST before acquire
atomic instructions without release semantics.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I893452450d430833e6c5a8e33a1e37b708218576
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931435

Cortex-A76AE erratum 1931435 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR_EL1[13] to 1. This bit
delays instruction fetch after branch misprediction. This workaround
will have a small impact on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I1baba8752f5f2e2ab5c873030e1f00cbb8cf1e60
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-A76AE erratum 1931427

Cortex-A76AE erratum 1931427 is a Cat B erratum that applies
to r0p0 and r1p0, it is fixed in r1p1.

This erratum can be avoided by setting CPUACTLR2_EL1[2] to 1. The bit
to force Atomic Store operations to write-back memory to be performed
in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1277541/1700/?lang=en

Change-Id: I31566838f894372e5627abda8b0bea1505f11f5d
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead o

docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead of using the common
Arm platform implementation.

Change-Id: I1eb8d262ba404f10a3cc2a0ff23bbc3f70041115
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by

docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>

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feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimi

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).

The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.

Note this will make object files unintepretable by objdump. Use lto-dump
instead.

BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).

Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind

docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3745f4506de123e3a4ff1e3ca6d5992f3b5c174a

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Merge "docs(n1sdp): update PSCI instrumentation data" into integration

docs(n1sdp): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: I74461f8ff009384c7db64a0a7f5b67a071a53334
Signed-off-by: Slava Andrianov <slava.andrianov@arm.co

docs(n1sdp): update PSCI instrumentation data

Update for v2.14 release based on v2.14-rc0

Change-Id: I74461f8ff009384c7db64a0a7f5b67a071a53334
Signed-off-by: Slava Andrianov <slava.andrianov@arm.com>

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feat(handoff): add firmware handoff threat model

Add threat model covering the Transfer List library (libTL) which
provides TF-A's implementation of the firmware handoff framework.

Change-Id: Idac6

feat(handoff): add firmware handoff threat model

Add threat model covering the Transfer List library (libTL) which
provides TF-A's implementation of the firmware handoff framework.

Change-Id: Idac6d5d423ed95bc4f0460a80007fd8d45976b19
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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