Merge changes from topic "feat_rme" into integration

* changes:
fix(firme): granule management service
feat(gpt): move gpt support under ENABLE_FEAT_RME
feat(rmmd): replace ENABLE_RME with ENA

Merge changes from topic "feat_rme" into integration

* changes:
fix(firme): granule management service
feat(gpt): move gpt support under ENABLE_FEAT_RME
feat(rmmd): replace ENABLE_RME with ENABLE_RMM
feat(rme): split off ENABLE_FEAT_RME

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Merge "fix(docs): use publicly accessible links for CVE-2023-49100 Advisory" into integration

fix(firme): granule management service

Report granule management service support and instances based on RME
support.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id:

fix(firme): granule management service

Report granule management service support and instances based on RME
support.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I5495df43914a495aa994c1475cb24e0d1322b7b0

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feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME rela

feat(gpt): move gpt support under ENABLE_FEAT_RME

Granule Protection Tables (GPT) library support is enabled only when
ENABLE_RMM is set (previously this build option was ENABLE_RME). Since
RME related support is now enabled using feature detection option
ENABLE_FEAT_RME, this patch moves GPT support under ENABLE_FEAT_RME.

This change brings in below benefits:
- single TF-A build that works for RME and non-RME systems, when
build with ENABLE_FEAT_RME=2 (FEAT_STATE_CHECK)
- RMM loading is optional on RME systems
- SiP calls that leverages RME features to change the PAS of a memory
range from non-secure to secure is supported without need to enable
Realm PAS or RMM.
- FIRME Granule Management Interface (GMI) ABIs that handles
FEAT_RME_GPC2/FEAT_RME_GDI can be enabled without need to enable RMM

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I88d9d4e0491af2b4ae0307c018f2d4a71ee6693f

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full

feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full RMM loading and handling.

While full CCA support requires all of these steps, some systems running
on FEAT_RME-capable cores do not need or want an RMM. However, such
systems still require TF-A page table entries to set the .NSE bit so
that TF-A accesses are correctly attributed to the ROOT world,
otherwise, enabling the MMU may cause the system to hang.

To address this, a new build option, ENABLE_FEAT_RME, is introduced. It
handles only the .NSE PTE setup and ignores the rest of the RME/RMM
initialization. ENABLE_FEAT_RME follows the ENABLE_FEAT_* convention and
supports values 0–2, with 2 enabling runtime detection.

Full RME functionality remains gated by ENABLE_RME, which now implicitly
enables ENABLE_FEAT_RME, allowing TF-A to run safely on FEAT_RME systems
without requiring an RMM.

Change-Id: I8391652842ff2e62a73b61829c6250c3805d4a4e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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docs(porting): add generic hold pen helpers

Add documentation for the plat_hold_pen_init(),
plat_hold_pen_signal(), and plat_hold_pen_wait_and_jump
helpers introduced in the generic hold pen refacto

docs(porting): add generic hold pen helpers

Add documentation for the plat_hold_pen_init(),
plat_hold_pen_signal(), and plat_hold_pen_wait_and_jump
helpers introduced in the generic hold pen refactoring.

Change-Id: Ic8c28ac6b8ba91e7aada31b49b592a637365fb9e
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

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feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces

feat(k3low): introduce Cadence LPDDR4 core driver for AM62L

AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces the
Cadence IP driver files (lpddr4.c, lpddr4_16bit.c, lpddr4_obj_if.c and
their associated headers) which carry dual copyright (Cadence + TI).

The driver was pruned from ~6800 macros to ~80 with AI-assisted removal
of unused code; the Cadence CTL/PHY/PI API surface remains intact for
review against the User Guides.

These files are intentionally unreferenced in platform.mk pending the
AM62L platform shim in the next patch.

For additional information please check the technical reference
manual at:
https://www.ti.com/lit/pdf/sprujb4

Change-Id: I8b02a6b30e5ea7b1b457cc0a933d8ef232993fa1
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

Merge "fix(rmmd): set RMM_V1_COMPAT=0" into integration

fix(rmmd): set RMM_V1_COMPAT=0

Set the default value of RMM_V1_COMPAT to 0. This means by default, TF-A
will only work with an RMM which is aligned to RMMv2.0 specification.

BREAKING-CHANGE: RMM v1

fix(rmmd): set RMM_V1_COMPAT=0

Set the default value of RMM_V1_COMPAT to 0. This means by default, TF-A
will only work with an RMM which is aligned to RMMv2.0 specification.

BREAKING-CHANGE: RMM v1.x compatibility is now disabled by default.
Platforms which continue to rely on the RMM v1 ABI must explicitly
build TF-A with `RMM_V1_COMPAT=1`.

Change-Id: Icf0e2dc9ebd8991cc989930807997625282191c3
Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>

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Merge "feat(firme): initial commit of FIRME service" into integration

feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic

feat(firme): initial commit of FIRME service

This is the first FIRME service patch that adds support for basic ABIs
for retrieving the FIRME version, features, and GPI_SET.

This adds a new generic granule transition function that replaces
the existing delegate/undelegate APIs that GPI_SET uses. It also
updates TRP to use GPI_SET when FIRME is supported.

FIRME spec is here, note that it is ALPHA2 quality so further changes
are to be expected:
https://developer.arm.com/documentation/den0149

Change-Id: I57b8ad7e87a0679e15c8247f8457f91f3254dedb
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(docs): use publicly accessible links for CVE-2023-49100 Advisory

The provided links are only available when signed in, switch to URLs
that are publicly accessible.

Fixes: d1eb4e2377c8 ("docs(se

fix(docs): use publicly accessible links for CVE-2023-49100 Advisory

The provided links are only available when signed in, switch to URLs
that are publicly accessible.

Fixes: d1eb4e2377c8 ("docs(security): security advisory for CVE-2023-49100")
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Change-Id: I9b201c5dba08b21c4ffd086875294ea2ae801f02

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Merge "docs(morello): update information regarding capability arch support" into integration

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(docs): do not describe BL arguments in as much detail" into integration

fix(docs): do not describe BL arguments in as much detail

This is a platform specific choice and as such out of scope for generic
code. It is also changing in relation to the use of transfer list so

fix(docs): do not describe BL arguments in as much detail

This is a platform specific choice and as such out of scope for generic
code. It is also changing in relation to the use of transfer list so it
may not even always be correct.

Change-Id: I3c170446341a2649297049edd157f85983812320
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for l

Merge changes from topic "qti_lemans_evk" into integration

* changes:
docs(qti): add lemans_evk platform documentation
fix(qti): don't panic() without QTISECLIB
feat(lemans): add support for lemans EVK platform
feat(qti): add support for Lemans SoC

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Merge "docs(maintainers): add code owner for Renesas RZ/A platform" into integration

docs(qti): add lemans_evk platform documentation

Add documentation for lemans_evk platform listing down step to
build, flash and boot up the platform with TF-A BL2 and BL31
support. Currently the QT

docs(qti): add lemans_evk platform documentation

Add documentation for lemans_evk platform listing down step to
build, flash and boot up the platform with TF-A BL2 and BL31
support. Currently the QTISECLIB port is work under progress,
hence the boot only progresses upto OP-TEE OS.

Change-Id: I9c01286511f7ee5ec4b758efe9068fd43858e5c5
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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docs(maintainers): add code owner for Renesas RZ/A platform

Add Nhut Nguyen as a code owner for Renesas RZ/A platform.

Change-Id: If22fcc8a7e1e464ab85a7dbce53faa1d7fc09f8b
Signed-off-by: Nhut Nguye

docs(maintainers): add code owner for Renesas RZ/A platform

Add Nhut Nguyen as a code owner for Renesas RZ/A platform.

Change-Id: If22fcc8a7e1e464ab85a7dbce53faa1d7fc09f8b
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

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docs(morello): update information regarding capability arch support

Update the information as per the lastest upstream code.

Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I450f7

docs(morello): update information regarding capability arch support

Update the information as per the lastest upstream code.

Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: I450f7a1600b88aacfd44950180c520aa45a19228

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Merge "refactor(nxp): add NXP_TBBR_USE_X509 switch for TBBR flow selection" into integration

Merge "test(bl): add short-read negative test scenario" into integration