1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_PRIVATE_H__ 8 #define __GICV2_PRIVATE_H__ 9 10 #include <gicv2.h> 11 #include <mmio.h> 12 #include <stdint.h> 13 14 /******************************************************************************* 15 * Private function prototypes 16 ******************************************************************************/ 17 void gicv2_spis_configure_defaults(uintptr_t gicd_base); 18 void gicv2_secure_spis_configure(uintptr_t gicd_base, 19 unsigned int num_ints, 20 const unsigned int *sec_intr_list); 21 void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, 22 unsigned int num_ints, 23 const unsigned int *sec_intr_list); 24 unsigned int gicv2_get_cpuif_id(uintptr_t base); 25 26 /******************************************************************************* 27 * GIC Distributor interface accessors for reading entire registers 28 ******************************************************************************/ 29 static inline unsigned int gicd_read_pidr2(uintptr_t base) 30 { 31 return mmio_read_32(base + GICD_PIDR2_GICV2); 32 } 33 34 /******************************************************************************* 35 * GIC Distributor interface accessors for writing entire registers 36 ******************************************************************************/ 37 static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id) 38 { 39 return mmio_read_8(base + GICD_ITARGETSR + id); 40 } 41 42 static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id, 43 unsigned int target) 44 { 45 mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); 46 } 47 48 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) 49 { 50 mmio_write_32(base + GICD_SGIR, val); 51 } 52 53 /******************************************************************************* 54 * GIC CPU interface accessors for reading entire registers 55 ******************************************************************************/ 56 57 static inline unsigned int gicc_read_ctlr(uintptr_t base) 58 { 59 return mmio_read_32(base + GICC_CTLR); 60 } 61 62 static inline unsigned int gicc_read_pmr(uintptr_t base) 63 { 64 return mmio_read_32(base + GICC_PMR); 65 } 66 67 static inline unsigned int gicc_read_BPR(uintptr_t base) 68 { 69 return mmio_read_32(base + GICC_BPR); 70 } 71 72 static inline unsigned int gicc_read_IAR(uintptr_t base) 73 { 74 return mmio_read_32(base + GICC_IAR); 75 } 76 77 static inline unsigned int gicc_read_EOIR(uintptr_t base) 78 { 79 return mmio_read_32(base + GICC_EOIR); 80 } 81 82 static inline unsigned int gicc_read_hppir(uintptr_t base) 83 { 84 return mmio_read_32(base + GICC_HPPIR); 85 } 86 87 static inline unsigned int gicc_read_ahppir(uintptr_t base) 88 { 89 return mmio_read_32(base + GICC_AHPPIR); 90 } 91 92 static inline unsigned int gicc_read_dir(uintptr_t base) 93 { 94 return mmio_read_32(base + GICC_DIR); 95 } 96 97 static inline unsigned int gicc_read_iidr(uintptr_t base) 98 { 99 return mmio_read_32(base + GICC_IIDR); 100 } 101 102 static inline unsigned int gicc_read_rpr(uintptr_t base) 103 { 104 return mmio_read_32(base + GICC_RPR); 105 } 106 107 /******************************************************************************* 108 * GIC CPU interface accessors for writing entire registers 109 ******************************************************************************/ 110 111 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) 112 { 113 mmio_write_32(base + GICC_CTLR, val); 114 } 115 116 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) 117 { 118 mmio_write_32(base + GICC_PMR, val); 119 } 120 121 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) 122 { 123 mmio_write_32(base + GICC_BPR, val); 124 } 125 126 127 static inline void gicc_write_IAR(uintptr_t base, unsigned int val) 128 { 129 mmio_write_32(base + GICC_IAR, val); 130 } 131 132 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) 133 { 134 mmio_write_32(base + GICC_EOIR, val); 135 } 136 137 static inline void gicc_write_hppir(uintptr_t base, unsigned int val) 138 { 139 mmio_write_32(base + GICC_HPPIR, val); 140 } 141 142 static inline void gicc_write_dir(uintptr_t base, unsigned int val) 143 { 144 mmio_write_32(base + GICC_DIR, val); 145 } 146 147 #endif /* __GICV2_PRIVATE_H__ */ 148