1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 #pragma weak plat_ic_is_spi 31 #pragma weak plat_ic_is_ppi 32 #pragma weak plat_ic_is_sgi 33 #pragma weak plat_ic_get_interrupt_active 34 #pragma weak plat_ic_enable_interrupt 35 #pragma weak plat_ic_disable_interrupt 36 37 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 38 (INTR_TYPE_NS == INTR_GROUP1NS) && 39 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 40 41 /* 42 * This function returns the highest priority pending interrupt at 43 * the Interrupt controller 44 */ 45 uint32_t plat_ic_get_pending_interrupt_id(void) 46 { 47 unsigned int irqnr; 48 49 assert(IS_IN_EL3()); 50 irqnr = gicv3_get_pending_interrupt_id(); 51 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 52 INTR_ID_UNAVAILABLE : irqnr; 53 } 54 55 /* 56 * This function returns the type of the highest priority pending interrupt 57 * at the Interrupt controller. In the case of GICv3, the Highest Priority 58 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 59 * the id of the pending interrupt. The type of interrupt depends upon the 60 * id value as follows. 61 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 62 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 63 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 64 * type. 65 * 4. All other interrupt id's are reported as EL3 interrupt. 66 */ 67 uint32_t plat_ic_get_pending_interrupt_type(void) 68 { 69 unsigned int irqnr; 70 71 assert(IS_IN_EL3()); 72 irqnr = gicv3_get_pending_interrupt_type(); 73 74 switch (irqnr) { 75 case PENDING_G1S_INTID: 76 return INTR_TYPE_S_EL1; 77 case PENDING_G1NS_INTID: 78 return INTR_TYPE_NS; 79 case GIC_SPURIOUS_INTERRUPT: 80 return INTR_TYPE_INVAL; 81 default: 82 return INTR_TYPE_EL3; 83 } 84 } 85 86 /* 87 * This function returns the highest priority pending interrupt at 88 * the Interrupt controller and indicates to the Interrupt controller 89 * that the interrupt processing has started. 90 */ 91 uint32_t plat_ic_acknowledge_interrupt(void) 92 { 93 assert(IS_IN_EL3()); 94 return gicv3_acknowledge_interrupt(); 95 } 96 97 /* 98 * This function returns the type of the interrupt `id`, depending on how 99 * the interrupt has been configured in the interrupt controller 100 */ 101 uint32_t plat_ic_get_interrupt_type(uint32_t id) 102 { 103 assert(IS_IN_EL3()); 104 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 105 } 106 107 /* 108 * This functions is used to indicate to the interrupt controller that 109 * the processing of the interrupt corresponding to the `id` has 110 * finished. 111 */ 112 void plat_ic_end_of_interrupt(uint32_t id) 113 { 114 assert(IS_IN_EL3()); 115 gicv3_end_of_interrupt(id); 116 } 117 118 /* 119 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 120 * The interrupt controller knows which pin/line it uses to signal a type of 121 * interrupt. It lets the interrupt management framework determine for a type of 122 * interrupt and security state, which line should be used in the SCR_EL3 to 123 * control its routing to EL3. The interrupt line is represented as the bit 124 * position of the IRQ or FIQ bit in the SCR_EL3. 125 */ 126 uint32_t plat_interrupt_type_to_line(uint32_t type, 127 uint32_t security_state) 128 { 129 assert(type == INTR_TYPE_S_EL1 || 130 type == INTR_TYPE_EL3 || 131 type == INTR_TYPE_NS); 132 133 assert(sec_state_is_valid(security_state)); 134 assert(IS_IN_EL3()); 135 136 switch (type) { 137 case INTR_TYPE_S_EL1: 138 /* 139 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 140 * and as FIQ in the NS-EL0/1/2 contexts 141 */ 142 if (security_state == SECURE) 143 return __builtin_ctz(SCR_IRQ_BIT); 144 else 145 return __builtin_ctz(SCR_FIQ_BIT); 146 case INTR_TYPE_NS: 147 /* 148 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 149 * contexts and as IRQ in the NS-EL0/1/2 contexts. 150 */ 151 if (security_state == SECURE) 152 return __builtin_ctz(SCR_FIQ_BIT); 153 else 154 return __builtin_ctz(SCR_IRQ_BIT); 155 default: 156 assert(0); 157 /* Fall through in the release build */ 158 case INTR_TYPE_EL3: 159 /* 160 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 161 * NS-EL0/1/2 contexts 162 */ 163 return __builtin_ctz(SCR_FIQ_BIT); 164 } 165 } 166 167 unsigned int plat_ic_get_running_priority(void) 168 { 169 return gicv3_get_running_priority(); 170 } 171 172 int plat_ic_is_spi(unsigned int id) 173 { 174 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 175 } 176 177 int plat_ic_is_ppi(unsigned int id) 178 { 179 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 180 } 181 182 int plat_ic_is_sgi(unsigned int id) 183 { 184 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 185 } 186 187 unsigned int plat_ic_get_interrupt_active(unsigned int id) 188 { 189 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 190 } 191 192 void plat_ic_enable_interrupt(unsigned int id) 193 { 194 gicv3_enable_interrupt(id, plat_my_core_pos()); 195 } 196 197 void plat_ic_disable_interrupt(unsigned int id) 198 { 199 gicv3_disable_interrupt(id, plat_my_core_pos()); 200 } 201 #endif 202 #ifdef IMAGE_BL32 203 204 #pragma weak plat_ic_get_pending_interrupt_id 205 #pragma weak plat_ic_acknowledge_interrupt 206 #pragma weak plat_ic_end_of_interrupt 207 208 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 209 #ifdef AARCH32 210 #define IS_IN_EL1() IS_IN_SECURE() 211 #endif 212 213 /* 214 * This function returns the highest priority pending interrupt at 215 * the Interrupt controller 216 */ 217 uint32_t plat_ic_get_pending_interrupt_id(void) 218 { 219 unsigned int irqnr; 220 221 assert(IS_IN_EL1()); 222 irqnr = gicv3_get_pending_interrupt_id_sel1(); 223 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 224 INTR_ID_UNAVAILABLE : irqnr; 225 } 226 227 /* 228 * This function returns the highest priority pending interrupt at 229 * the Interrupt controller and indicates to the Interrupt controller 230 * that the interrupt processing has started. 231 */ 232 uint32_t plat_ic_acknowledge_interrupt(void) 233 { 234 assert(IS_IN_EL1()); 235 return gicv3_acknowledge_interrupt_sel1(); 236 } 237 238 /* 239 * This functions is used to indicate to the interrupt controller that 240 * the processing of the interrupt corresponding to the `id` has 241 * finished. 242 */ 243 void plat_ic_end_of_interrupt(uint32_t id) 244 { 245 assert(IS_IN_EL1()); 246 gicv3_end_of_interrupt_sel1(id); 247 } 248 #endif 249