1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include "../common/gic_common_private.h" 13 #include "gicv3_private.h" 14 15 /* 16 * Accessor to read the GIC Distributor IGRPMODR corresponding to the 17 * interrupt `id`, 32 interrupt IDs at a time. 18 */ 19 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) 20 { 21 unsigned n = id >> IGRPMODR_SHIFT; 22 return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); 23 } 24 25 /* 26 * Accessor to write the GIC Distributor IGRPMODR corresponding to the 27 * interrupt `id`, 32 interrupt IDs at a time. 28 */ 29 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) 30 { 31 unsigned n = id >> IGRPMODR_SHIFT; 32 mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); 33 } 34 35 /* 36 * Accessor to get the bit corresponding to interrupt ID 37 * in GIC Distributor IGRPMODR. 38 */ 39 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) 40 { 41 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 42 unsigned int reg_val = gicd_read_igrpmodr(base, id); 43 44 return (reg_val >> bit_num) & 0x1; 45 } 46 47 /* 48 * Accessor to set the bit corresponding to interrupt ID 49 * in GIC Distributor IGRPMODR. 50 */ 51 void gicd_set_igrpmodr(uintptr_t base, unsigned int id) 52 { 53 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 54 unsigned int reg_val = gicd_read_igrpmodr(base, id); 55 56 gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num)); 57 } 58 59 /* 60 * Accessor to clear the bit corresponding to interrupt ID 61 * in GIC Distributor IGRPMODR. 62 */ 63 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) 64 { 65 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 66 unsigned int reg_val = gicd_read_igrpmodr(base, id); 67 68 gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num)); 69 } 70 71 /* 72 * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the 73 * interrupt `id`, 4 interrupts IDs at a time. 74 */ 75 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) 76 { 77 unsigned n = id >> IPRIORITYR_SHIFT; 78 return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); 79 } 80 81 /* 82 * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the 83 * interrupt `id`, 4 interrupts IDs at a time. 84 */ 85 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) 86 { 87 unsigned n = id >> IPRIORITYR_SHIFT; 88 mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); 89 } 90 91 /* 92 * Accessor to get the bit corresponding to interrupt ID 93 * from GIC Re-distributor IGROUPR0. 94 */ 95 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) 96 { 97 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 98 unsigned int reg_val = gicr_read_igroupr0(base); 99 100 return (reg_val >> bit_num) & 0x1; 101 } 102 103 /* 104 * Accessor to set the bit corresponding to interrupt ID 105 * in GIC Re-distributor IGROUPR0. 106 */ 107 void gicr_set_igroupr0(uintptr_t base, unsigned int id) 108 { 109 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 110 unsigned int reg_val = gicr_read_igroupr0(base); 111 112 gicr_write_igroupr0(base, reg_val | (1 << bit_num)); 113 } 114 115 /* 116 * Accessor to clear the bit corresponding to interrupt ID 117 * in GIC Re-distributor IGROUPR0. 118 */ 119 void gicr_clr_igroupr0(uintptr_t base, unsigned int id) 120 { 121 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 122 unsigned int reg_val = gicr_read_igroupr0(base); 123 124 gicr_write_igroupr0(base, reg_val & ~(1 << bit_num)); 125 } 126 127 /* 128 * Accessor to get the bit corresponding to interrupt ID 129 * from GIC Re-distributor IGRPMODR0. 130 */ 131 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) 132 { 133 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 134 unsigned int reg_val = gicr_read_igrpmodr0(base); 135 136 return (reg_val >> bit_num) & 0x1; 137 } 138 139 /* 140 * Accessor to set the bit corresponding to interrupt ID 141 * in GIC Re-distributor IGRPMODR0. 142 */ 143 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) 144 { 145 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 146 unsigned int reg_val = gicr_read_igrpmodr0(base); 147 148 gicr_write_igrpmodr0(base, reg_val | (1 << bit_num)); 149 } 150 151 /* 152 * Accessor to clear the bit corresponding to interrupt ID 153 * in GIC Re-distributor IGRPMODR0. 154 */ 155 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) 156 { 157 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 158 unsigned int reg_val = gicr_read_igrpmodr0(base); 159 160 gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num)); 161 } 162 163 /* 164 * Accessor to set the bit corresponding to interrupt ID 165 * in GIC Re-distributor ISENABLER0. 166 */ 167 void gicr_set_isenabler0(uintptr_t base, unsigned int id) 168 { 169 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); 170 171 gicr_write_isenabler0(base, (1 << bit_num)); 172 } 173 174 /* 175 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 176 * ISACTIVER0. 177 */ 178 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id) 179 { 180 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); 181 unsigned int reg_val = gicr_read_isactiver0(base); 182 183 return (reg_val >> bit_num) & 0x1; 184 } 185 186 /* 187 * Accessor to set the byte corresponding to interrupt ID 188 * in GIC Re-distributor IPRIORITYR. 189 */ 190 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) 191 { 192 mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); 193 } 194 195 /****************************************************************************** 196 * This function marks the core as awake in the re-distributor and 197 * ensures that the interface is active. 198 *****************************************************************************/ 199 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 200 { 201 /* 202 * The WAKER_PS_BIT should be changed to 0 203 * only when WAKER_CA_BIT is 1. 204 */ 205 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); 206 207 /* Mark the connected core as awake */ 208 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 209 210 /* Wait till the WAKER_CA_BIT changes to 0 */ 211 while (gicr_read_waker(gicr_base) & WAKER_CA_BIT) 212 ; 213 } 214 215 216 /****************************************************************************** 217 * This function marks the core as asleep in the re-distributor and ensures 218 * that the interface is quiescent. 219 *****************************************************************************/ 220 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 221 { 222 /* Mark the connected core as asleep */ 223 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 224 225 /* Wait till the WAKER_CA_BIT changes to 1 */ 226 while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT)) 227 ; 228 } 229 230 231 /******************************************************************************* 232 * This function probes the Redistributor frames when the driver is initialised 233 * and saves their base addresses. These base addresses are used later to 234 * initialise each Redistributor interface. 235 ******************************************************************************/ 236 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 237 unsigned int rdistif_num, 238 uintptr_t gicr_base, 239 mpidr_hash_fn mpidr_to_core_pos) 240 { 241 u_register_t mpidr; 242 unsigned int proc_num; 243 unsigned long long typer_val; 244 uintptr_t rdistif_base = gicr_base; 245 246 assert(rdistif_base_addrs); 247 248 /* 249 * Iterate over the Redistributor frames. Store the base address of each 250 * frame in the platform provided array. Use the "Processor Number" 251 * field to index into the array if the platform has not provided a hash 252 * function to convert an MPIDR (obtained from the "Affinity Value" 253 * field into a linear index. 254 */ 255 do { 256 typer_val = gicr_read_typer(rdistif_base); 257 if (mpidr_to_core_pos) { 258 mpidr = mpidr_from_gicr_typer(typer_val); 259 proc_num = mpidr_to_core_pos(mpidr); 260 } else { 261 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 262 TYPER_PROC_NUM_MASK; 263 } 264 assert(proc_num < rdistif_num); 265 rdistif_base_addrs[proc_num] = rdistif_base; 266 rdistif_base += (1 << GICR_PCPUBASE_SHIFT); 267 } while (!(typer_val & TYPER_LAST_BIT)); 268 } 269 270 /******************************************************************************* 271 * Helper function to configure the default attributes of SPIs. 272 ******************************************************************************/ 273 void gicv3_spis_configure_defaults(uintptr_t gicd_base) 274 { 275 unsigned int index, num_ints; 276 277 num_ints = gicd_read_typer(gicd_base); 278 num_ints &= TYPER_IT_LINES_NO_MASK; 279 num_ints = (num_ints + 1) << 5; 280 281 /* 282 * Treat all SPIs as G1NS by default. The number of interrupts is 283 * calculated as 32 * (IT_LINES + 1). We do 32 at a time. 284 */ 285 for (index = MIN_SPI_ID; index < num_ints; index += 32) 286 gicd_write_igroupr(gicd_base, index, ~0U); 287 288 /* Setup the default SPI priorities doing four at a time */ 289 for (index = MIN_SPI_ID; index < num_ints; index += 4) 290 gicd_write_ipriorityr(gicd_base, 291 index, 292 GICD_IPRIORITYR_DEF_VAL); 293 294 /* 295 * Treat all SPIs as level triggered by default, write 16 at 296 * a time 297 */ 298 for (index = MIN_SPI_ID; index < num_ints; index += 16) 299 gicd_write_icfgr(gicd_base, index, 0); 300 } 301 302 /******************************************************************************* 303 * Helper function to configure secure G0 and G1S SPIs. 304 ******************************************************************************/ 305 void gicv3_secure_spis_configure(uintptr_t gicd_base, 306 unsigned int num_ints, 307 const unsigned int *sec_intr_list, 308 unsigned int int_grp) 309 { 310 unsigned int index, irq_num; 311 unsigned long long gic_affinity_val; 312 313 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 314 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 315 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 316 317 for (index = 0; index < num_ints; index++) { 318 irq_num = sec_intr_list[index]; 319 if (irq_num >= MIN_SPI_ID) { 320 321 /* Configure this interrupt as a secure interrupt */ 322 gicd_clr_igroupr(gicd_base, irq_num); 323 324 /* Configure this interrupt as G0 or a G1S interrupt */ 325 if (int_grp == INTR_GROUP1S) 326 gicd_set_igrpmodr(gicd_base, irq_num); 327 else 328 gicd_clr_igrpmodr(gicd_base, irq_num); 329 330 /* Set the priority of this interrupt */ 331 gicd_set_ipriorityr(gicd_base, 332 irq_num, 333 GIC_HIGHEST_SEC_PRIORITY); 334 335 /* Target SPIs to the primary CPU */ 336 gic_affinity_val = 337 gicd_irouter_val_from_mpidr(read_mpidr(), 0); 338 gicd_write_irouter(gicd_base, 339 irq_num, 340 gic_affinity_val); 341 342 /* Enable this interrupt */ 343 gicd_set_isenabler(gicd_base, irq_num); 344 } 345 } 346 347 } 348 349 /******************************************************************************* 350 * Helper function to configure the default attributes of SPIs. 351 ******************************************************************************/ 352 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base) 353 { 354 unsigned int index; 355 356 /* 357 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 358 * more scalable approach as it avoids clearing the enable bits in the 359 * GICD_CTLR 360 */ 361 gicr_write_icenabler0(gicr_base, ~0); 362 gicr_wait_for_pending_write(gicr_base); 363 364 /* Treat all SGIs/PPIs as G1NS by default. */ 365 gicr_write_igroupr0(gicr_base, ~0U); 366 367 /* Setup the default PPI/SGI priorities doing four at a time */ 368 for (index = 0; index < MIN_SPI_ID; index += 4) 369 gicr_write_ipriorityr(gicr_base, 370 index, 371 GICD_IPRIORITYR_DEF_VAL); 372 373 /* Configure all PPIs as level triggered by default */ 374 gicr_write_icfgr1(gicr_base, 0); 375 } 376 377 /******************************************************************************* 378 * Helper function to configure secure G0 and G1S SPIs. 379 ******************************************************************************/ 380 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 381 unsigned int num_ints, 382 const unsigned int *sec_intr_list, 383 unsigned int int_grp) 384 { 385 unsigned int index, irq_num; 386 387 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 388 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 389 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 390 391 for (index = 0; index < num_ints; index++) { 392 irq_num = sec_intr_list[index]; 393 if (irq_num < MIN_SPI_ID) { 394 395 /* Configure this interrupt as a secure interrupt */ 396 gicr_clr_igroupr0(gicr_base, irq_num); 397 398 /* Configure this interrupt as G0 or a G1S interrupt */ 399 if (int_grp == INTR_GROUP1S) 400 gicr_set_igrpmodr0(gicr_base, irq_num); 401 else 402 gicr_clr_igrpmodr0(gicr_base, irq_num); 403 404 /* Set the priority of this interrupt */ 405 gicr_set_ipriorityr(gicr_base, 406 irq_num, 407 GIC_HIGHEST_SEC_PRIORITY); 408 409 /* Enable this interrupt */ 410 gicr_set_isenabler0(gicr_base, irq_num); 411 } 412 } 413 } 414