1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_PRIVATE_H__ 8 #define __GICV3_PRIVATE_H__ 9 10 #include <assert.h> 11 #include <gic_common.h> 12 #include <gicv3.h> 13 #include <mmio.h> 14 #include <stdint.h> 15 #include "../common/gic_common_private.h" 16 17 /******************************************************************************* 18 * GICv3 private macro definitions 19 ******************************************************************************/ 20 21 /* Constants to indicate the status of the RWP bit */ 22 #define RWP_TRUE 1 23 #define RWP_FALSE 0 24 25 /* 26 * Macro to convert an mpidr to a value suitable for programming into a 27 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 28 * to GICv3. 29 */ 30 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 31 ((mpidr & ~(0xff << 24)) | \ 32 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 33 34 /* 35 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 36 * are zeroes. 37 */ 38 #ifdef AARCH32 39 #define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff) 40 #else 41 #define mpidr_from_gicr_typer(typer_val) \ 42 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 43 (((typer_val) >> 32) & 0xffffff)) 44 #endif 45 46 /******************************************************************************* 47 * GICv3 private global variables declarations 48 ******************************************************************************/ 49 extern const gicv3_driver_data_t *gicv3_driver_data; 50 51 /******************************************************************************* 52 * Private GICv3 function prototypes for accessing entire registers. 53 * Note: The raw register values correspond to multiple interrupt IDs and 54 * the number of interrupt IDs involved depends on the register accessed. 55 ******************************************************************************/ 56 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 57 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 58 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 59 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 60 61 /******************************************************************************* 62 * Private GICv3 function prototypes for accessing the GIC registers 63 * corresponding to a single interrupt ID. These functions use bitwise 64 * operations or appropriate register accesses to modify or return 65 * the bit-field corresponding the single interrupt ID. 66 ******************************************************************************/ 67 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 68 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 69 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 70 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id); 71 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 72 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 73 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 74 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 75 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 76 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 77 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 78 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 79 80 /******************************************************************************* 81 * Private GICv3 helper function prototypes 82 ******************************************************************************/ 83 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 84 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 85 void gicv3_secure_spis_configure(uintptr_t gicd_base, 86 unsigned int num_ints, 87 const unsigned int *sec_intr_list, 88 unsigned int int_grp); 89 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 90 unsigned int num_ints, 91 const unsigned int *sec_intr_list, 92 unsigned int int_grp); 93 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 94 unsigned int rdistif_num, 95 uintptr_t gicr_base, 96 mpidr_hash_fn mpidr_to_core_pos); 97 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 98 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 99 100 /******************************************************************************* 101 * GIC Distributor interface accessors 102 ******************************************************************************/ 103 /* 104 * Wait for updates to : 105 * GICD_CTLR[2:0] - the Group Enables 106 * GICD_CTLR[5:4] - the ARE bits 107 * GICD_ICENABLERn - the clearing of enable state for SPIs 108 */ 109 static inline void gicd_wait_for_pending_write(uintptr_t gicd_base) 110 { 111 while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 112 ; 113 } 114 115 static inline unsigned int gicd_read_pidr2(uintptr_t base) 116 { 117 return mmio_read_32(base + GICD_PIDR2_GICV3); 118 } 119 120 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 121 { 122 assert(id >= MIN_SPI_ID); 123 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 124 } 125 126 static inline void gicd_write_irouter(uintptr_t base, 127 unsigned int id, 128 unsigned long long affinity) 129 { 130 assert(id >= MIN_SPI_ID); 131 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 132 } 133 134 static inline void gicd_clr_ctlr(uintptr_t base, 135 unsigned int bitmap, 136 unsigned int rwp) 137 { 138 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 139 if (rwp) 140 gicd_wait_for_pending_write(base); 141 } 142 143 static inline void gicd_set_ctlr(uintptr_t base, 144 unsigned int bitmap, 145 unsigned int rwp) 146 { 147 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 148 if (rwp) 149 gicd_wait_for_pending_write(base); 150 } 151 152 /******************************************************************************* 153 * GIC Redistributor interface accessors 154 ******************************************************************************/ 155 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 156 { 157 return mmio_read_64(base + GICR_CTLR); 158 } 159 160 static inline void gicr_write_ctlr(uintptr_t base, uint64_t val) 161 { 162 mmio_write_64(base + GICR_CTLR, val); 163 } 164 165 static inline unsigned long long gicr_read_typer(uintptr_t base) 166 { 167 return mmio_read_64(base + GICR_TYPER); 168 } 169 170 static inline unsigned int gicr_read_waker(uintptr_t base) 171 { 172 return mmio_read_32(base + GICR_WAKER); 173 } 174 175 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 176 { 177 mmio_write_32(base + GICR_WAKER, val); 178 } 179 180 /* 181 * Wait for updates to : 182 * GICR_ICENABLER0 183 * GICR_CTLR.DPG1S 184 * GICR_CTLR.DPG1NS 185 * GICR_CTLR.DPG0 186 */ 187 static inline void gicr_wait_for_pending_write(uintptr_t gicr_base) 188 { 189 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 190 ; 191 } 192 193 static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base) 194 { 195 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT) 196 ; 197 } 198 199 /* Private implementation of Distributor power control hooks */ 200 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num); 201 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num); 202 203 /******************************************************************************* 204 * GIC Re-distributor functions for accessing entire registers. 205 * Note: The raw register values correspond to multiple interrupt IDs and 206 * the number of interrupt IDs involved depends on the register accessed. 207 ******************************************************************************/ 208 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 209 { 210 return mmio_read_32(base + GICR_ICENABLER0); 211 } 212 213 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 214 { 215 mmio_write_32(base + GICR_ICENABLER0, val); 216 } 217 218 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 219 { 220 return mmio_read_32(base + GICR_ISENABLER0); 221 } 222 223 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 224 { 225 mmio_write_32(base + GICR_ISENABLER0, val); 226 } 227 228 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 229 { 230 return mmio_read_32(base + GICR_IGROUPR0); 231 } 232 233 static inline unsigned int gicr_read_ispendr0(uintptr_t base) 234 { 235 return mmio_read_32(base + GICR_ISPENDR0); 236 } 237 238 static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val) 239 { 240 mmio_write_32(base + GICR_ISPENDR0, val); 241 } 242 243 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 244 { 245 mmio_write_32(base + GICR_IGROUPR0, val); 246 } 247 248 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 249 { 250 return mmio_read_32(base + GICR_IGRPMODR0); 251 } 252 253 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 254 { 255 mmio_write_32(base + GICR_IGRPMODR0, val); 256 } 257 258 static inline unsigned int gicr_read_nsacr(uintptr_t base) 259 { 260 return mmio_read_32(base + GICR_NSACR); 261 } 262 263 static inline void gicr_write_nsacr(uintptr_t base, unsigned int val) 264 { 265 mmio_write_32(base + GICR_NSACR, val); 266 } 267 268 static inline unsigned int gicr_read_isactiver0(uintptr_t base) 269 { 270 return mmio_read_32(base + GICR_ISACTIVER0); 271 } 272 273 static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val) 274 { 275 mmio_write_32(base + GICR_ISACTIVER0, val); 276 } 277 278 static inline unsigned int gicr_read_icfgr0(uintptr_t base) 279 { 280 return mmio_read_32(base + GICR_ICFGR0); 281 } 282 283 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 284 { 285 return mmio_read_32(base + GICR_ICFGR1); 286 } 287 288 static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val) 289 { 290 mmio_write_32(base + GICR_ICFGR0, val); 291 } 292 293 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 294 { 295 mmio_write_32(base + GICR_ICFGR1, val); 296 } 297 298 static inline unsigned int gicr_read_propbaser(uintptr_t base) 299 { 300 return mmio_read_32(base + GICR_PROPBASER); 301 } 302 303 static inline void gicr_write_propbaser(uintptr_t base, unsigned int val) 304 { 305 mmio_write_32(base + GICR_PROPBASER, val); 306 } 307 308 static inline unsigned int gicr_read_pendbaser(uintptr_t base) 309 { 310 return mmio_read_32(base + GICR_PENDBASER); 311 } 312 313 static inline void gicr_write_pendbaser(uintptr_t base, unsigned int val) 314 { 315 mmio_write_32(base + GICR_PENDBASER, val); 316 } 317 318 /******************************************************************************* 319 * GIC ITS functions to read and write entire ITS registers. 320 ******************************************************************************/ 321 static inline uint32_t gits_read_ctlr(uintptr_t base) 322 { 323 return mmio_read_32(base + GITS_CTLR); 324 } 325 326 static inline void gits_write_ctlr(uintptr_t base, unsigned int val) 327 { 328 mmio_write_32(base + GITS_CTLR, val); 329 } 330 331 static inline uint64_t gits_read_cbaser(uintptr_t base) 332 { 333 return mmio_read_64(base + GITS_CBASER); 334 } 335 336 static inline void gits_write_cbaser(uintptr_t base, uint64_t val) 337 { 338 mmio_write_32(base + GITS_CBASER, val); 339 } 340 341 static inline uint64_t gits_read_cwriter(uintptr_t base) 342 { 343 return mmio_read_64(base + GITS_CWRITER); 344 } 345 346 static inline void gits_write_cwriter(uintptr_t base, uint64_t val) 347 { 348 mmio_write_32(base + GITS_CWRITER, val); 349 } 350 351 static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id) 352 { 353 assert(its_table_id < 8); 354 return mmio_read_64(base + GITS_BASER + (8 * its_table_id)); 355 } 356 357 static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val) 358 { 359 assert(its_table_id < 8); 360 mmio_write_64(base + GITS_BASER + (8 * its_table_id), val); 361 } 362 363 /* 364 * Wait for Quiescent bit when GIC ITS is disabled 365 */ 366 static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base) 367 { 368 assert(!(gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT)); 369 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0) 370 ; 371 } 372 373 374 #endif /* __GICV3_PRIVATE_H__ */ 375