1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <gic_common.h> 8 #include <gicv2.h> 9 #include <interrupt_mgmt.h> 10 11 /* 12 * The following platform GIC functions are weakly defined. They 13 * provide typical implementations that may be re-used by multiple 14 * platforms but may also be overridden by a platform if required. 15 */ 16 #pragma weak plat_ic_get_pending_interrupt_id 17 #pragma weak plat_ic_get_pending_interrupt_type 18 #pragma weak plat_ic_acknowledge_interrupt 19 #pragma weak plat_ic_get_interrupt_type 20 #pragma weak plat_ic_end_of_interrupt 21 #pragma weak plat_interrupt_type_to_line 22 23 #pragma weak plat_ic_get_running_priority 24 #pragma weak plat_ic_is_spi 25 #pragma weak plat_ic_is_ppi 26 #pragma weak plat_ic_is_sgi 27 28 /* 29 * This function returns the highest priority pending interrupt at 30 * the Interrupt controller 31 */ 32 uint32_t plat_ic_get_pending_interrupt_id(void) 33 { 34 unsigned int id; 35 36 id = gicv2_get_pending_interrupt_id(); 37 if (id == GIC_SPURIOUS_INTERRUPT) 38 return INTR_ID_UNAVAILABLE; 39 40 return id; 41 } 42 43 /* 44 * This function returns the type of the highest priority pending interrupt 45 * at the Interrupt controller. In the case of GICv2, the Highest Priority 46 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 47 * the pending interrupt. The type of interrupt depends upon the id value 48 * as follows. 49 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 50 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 51 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 52 * type. 53 */ 54 uint32_t plat_ic_get_pending_interrupt_type(void) 55 { 56 unsigned int id; 57 58 id = gicv2_get_pending_interrupt_type(); 59 60 /* Assume that all secure interrupts are S-EL1 interrupts */ 61 if (id < PENDING_G1_INTID) 62 return INTR_TYPE_S_EL1; 63 64 if (id == GIC_SPURIOUS_INTERRUPT) 65 return INTR_TYPE_INVAL; 66 67 return INTR_TYPE_NS; 68 } 69 70 /* 71 * This function returns the highest priority pending interrupt at 72 * the Interrupt controller and indicates to the Interrupt controller 73 * that the interrupt processing has started. 74 */ 75 uint32_t plat_ic_acknowledge_interrupt(void) 76 { 77 return gicv2_acknowledge_interrupt(); 78 } 79 80 /* 81 * This function returns the type of the interrupt `id`, depending on how 82 * the interrupt has been configured in the interrupt controller 83 */ 84 uint32_t plat_ic_get_interrupt_type(uint32_t id) 85 { 86 unsigned int type; 87 88 type = gicv2_get_interrupt_group(id); 89 90 /* Assume that all secure interrupts are S-EL1 interrupts */ 91 return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1; 92 } 93 94 /* 95 * This functions is used to indicate to the interrupt controller that 96 * the processing of the interrupt corresponding to the `id` has 97 * finished. 98 */ 99 void plat_ic_end_of_interrupt(uint32_t id) 100 { 101 gicv2_end_of_interrupt(id); 102 } 103 104 /* 105 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 106 * The interrupt controller knows which pin/line it uses to signal a type of 107 * interrupt. It lets the interrupt management framework determine 108 * for a type of interrupt and security state, which line should be used in the 109 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 110 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 111 */ 112 uint32_t plat_interrupt_type_to_line(uint32_t type, 113 uint32_t security_state) 114 { 115 assert(type == INTR_TYPE_S_EL1 || 116 type == INTR_TYPE_EL3 || 117 type == INTR_TYPE_NS); 118 119 /* Non-secure interrupts are signaled on the IRQ line always */ 120 if (type == INTR_TYPE_NS) 121 return __builtin_ctz(SCR_IRQ_BIT); 122 123 /* 124 * Secure interrupts are signaled using the IRQ line if the FIQ is 125 * not enabled else they are signaled using the FIQ line. 126 */ 127 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : 128 __builtin_ctz(SCR_IRQ_BIT)); 129 } 130 131 unsigned int plat_ic_get_running_priority(void) 132 { 133 return gicv2_get_running_priority(); 134 } 135 136 int plat_ic_is_spi(unsigned int id) 137 { 138 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 139 } 140 141 int plat_ic_is_ppi(unsigned int id) 142 { 143 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 144 } 145 146 int plat_ic_is_sgi(unsigned int id) 147 { 148 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 149 } 150