1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_H__ 8 #define __GICV2_H__ 9 10 /******************************************************************************* 11 * GICv2 miscellaneous definitions 12 ******************************************************************************/ 13 14 /* Interrupt group definitions */ 15 #define GICV2_INTR_GROUP0 0 16 #define GICV2_INTR_GROUP1 1 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1_INTID 1022 20 21 /* GICv2 can only target up to 8 PEs */ 22 #define GICV2_MAX_TARGET_PE 8 23 24 /******************************************************************************* 25 * GICv2 specific Distributor interface register offsets and constants. 26 ******************************************************************************/ 27 #define GICD_ITARGETSR 0x800 28 #define GICD_SGIR 0xF00 29 #define GICD_CPENDSGIR 0xF10 30 #define GICD_SPENDSGIR 0xF20 31 #define GICD_PIDR2_GICV2 0xFE8 32 33 #define ITARGETSR_SHIFT 2 34 #define GIC_TARGET_CPU_MASK 0xff 35 36 #define CPENDSGIR_SHIFT 2 37 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 38 39 /******************************************************************************* 40 * GICv2 specific CPU interface register offsets and constants. 41 ******************************************************************************/ 42 /* Physical CPU Interface registers */ 43 #define GICC_CTLR 0x0 44 #define GICC_PMR 0x4 45 #define GICC_BPR 0x8 46 #define GICC_IAR 0xC 47 #define GICC_EOIR 0x10 48 #define GICC_RPR 0x14 49 #define GICC_HPPIR 0x18 50 #define GICC_AHPPIR 0x28 51 #define GICC_IIDR 0xFC 52 #define GICC_DIR 0x1000 53 #define GICC_PRIODROP GICC_EOIR 54 55 /* GICC_CTLR bit definitions */ 56 #define EOI_MODE_NS (1 << 10) 57 #define EOI_MODE_S (1 << 9) 58 #define IRQ_BYP_DIS_GRP1 (1 << 8) 59 #define FIQ_BYP_DIS_GRP1 (1 << 7) 60 #define IRQ_BYP_DIS_GRP0 (1 << 6) 61 #define FIQ_BYP_DIS_GRP0 (1 << 5) 62 #define CBPR (1 << 4) 63 #define FIQ_EN_SHIFT 3 64 #define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) 65 #define ACK_CTL (1 << 2) 66 67 /* GICC_IIDR bit masks and shifts */ 68 #define GICC_IIDR_PID_SHIFT 20 69 #define GICC_IIDR_ARCH_SHIFT 16 70 #define GICC_IIDR_REV_SHIFT 12 71 #define GICC_IIDR_IMP_SHIFT 0 72 73 #define GICC_IIDR_PID_MASK 0xfff 74 #define GICC_IIDR_ARCH_MASK 0xf 75 #define GICC_IIDR_REV_MASK 0xf 76 #define GICC_IIDR_IMP_MASK 0xfff 77 78 /* HYP view virtual CPU Interface registers */ 79 #define GICH_CTL 0x0 80 #define GICH_VTR 0x4 81 #define GICH_ELRSR0 0x30 82 #define GICH_ELRSR1 0x34 83 #define GICH_APR0 0xF0 84 #define GICH_LR_BASE 0x100 85 86 /* Virtual CPU Interface registers */ 87 #define GICV_CTL 0x0 88 #define GICV_PRIMASK 0x4 89 #define GICV_BP 0x8 90 #define GICV_INTACK 0xC 91 #define GICV_EOI 0x10 92 #define GICV_RUNNINGPRI 0x14 93 #define GICV_HIGHESTPEND 0x18 94 #define GICV_DEACTIVATE 0x1000 95 96 /* GICD_CTLR bit definitions */ 97 #define CTLR_ENABLE_G1_SHIFT 1 98 #define CTLR_ENABLE_G1_MASK 0x1 99 #define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) 100 101 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 102 #define INT_ID_MASK 0x3ff 103 104 #ifndef __ASSEMBLY__ 105 106 #include <stdint.h> 107 108 /******************************************************************************* 109 * This structure describes some of the implementation defined attributes of 110 * the GICv2 IP. It is used by the platform port to specify these attributes 111 * in order to initialize the GICv2 driver. The attributes are described 112 * below. 113 * 114 * The 'gicd_base' field contains the base address of the Distributor interface 115 * programmer's view. 116 * 117 * The 'gicc_base' field contains the base address of the CPU Interface 118 * programmer's view. 119 * 120 * The 'g0_interrupt_array' field is a pointer to an array in which each 121 * entry corresponds to an ID of a Group 0 interrupt. 122 * 123 * The 'g0_interrupt_num' field contains the number of entries in the 124 * 'g0_interrupt_array'. 125 * 126 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 127 * elements. The GIC driver will populate the array with per-PE target mask to 128 * use to when targeting interrupts. 129 ******************************************************************************/ 130 typedef struct gicv2_driver_data { 131 uintptr_t gicd_base; 132 uintptr_t gicc_base; 133 unsigned int g0_interrupt_num; 134 const unsigned int *g0_interrupt_array; 135 unsigned int *target_masks; 136 unsigned int target_masks_num; 137 } gicv2_driver_data_t; 138 139 /******************************************************************************* 140 * Function prototypes 141 ******************************************************************************/ 142 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 143 void gicv2_distif_init(void); 144 void gicv2_pcpu_distif_init(void); 145 void gicv2_cpuif_enable(void); 146 void gicv2_cpuif_disable(void); 147 unsigned int gicv2_is_fiq_enabled(void); 148 unsigned int gicv2_get_pending_interrupt_type(void); 149 unsigned int gicv2_get_pending_interrupt_id(void); 150 unsigned int gicv2_acknowledge_interrupt(void); 151 void gicv2_end_of_interrupt(unsigned int id); 152 unsigned int gicv2_get_interrupt_group(unsigned int id); 153 unsigned int gicv2_get_running_priority(void); 154 void gicv2_set_pe_target_mask(unsigned int proc_num); 155 unsigned int gicv2_get_interrupt_active(unsigned int id); 156 void gicv2_enable_interrupt(unsigned int id); 157 void gicv2_disable_interrupt(unsigned int id); 158 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); 159 void gicv2_set_interrupt_type(unsigned int id, unsigned int type); 160 161 #endif /* __ASSEMBLY__ */ 162 #endif /* __GICV2_H__ */ 163