1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include "../common/gic_common_private.h" 13 #include "gicv3_private.h" 14 15 /* 16 * Accessor to read the GIC Distributor IGRPMODR corresponding to the 17 * interrupt `id`, 32 interrupt IDs at a time. 18 */ 19 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) 20 { 21 unsigned n = id >> IGRPMODR_SHIFT; 22 return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); 23 } 24 25 /* 26 * Accessor to write the GIC Distributor IGRPMODR corresponding to the 27 * interrupt `id`, 32 interrupt IDs at a time. 28 */ 29 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) 30 { 31 unsigned n = id >> IGRPMODR_SHIFT; 32 mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); 33 } 34 35 /* 36 * Accessor to get the bit corresponding to interrupt ID 37 * in GIC Distributor IGRPMODR. 38 */ 39 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) 40 { 41 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 42 unsigned int reg_val = gicd_read_igrpmodr(base, id); 43 44 return (reg_val >> bit_num) & 0x1; 45 } 46 47 /* 48 * Accessor to set the bit corresponding to interrupt ID 49 * in GIC Distributor IGRPMODR. 50 */ 51 void gicd_set_igrpmodr(uintptr_t base, unsigned int id) 52 { 53 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 54 unsigned int reg_val = gicd_read_igrpmodr(base, id); 55 56 gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num)); 57 } 58 59 /* 60 * Accessor to clear the bit corresponding to interrupt ID 61 * in GIC Distributor IGRPMODR. 62 */ 63 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) 64 { 65 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 66 unsigned int reg_val = gicd_read_igrpmodr(base, id); 67 68 gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num)); 69 } 70 71 /* 72 * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the 73 * interrupt `id`, 4 interrupts IDs at a time. 74 */ 75 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) 76 { 77 unsigned n = id >> IPRIORITYR_SHIFT; 78 return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); 79 } 80 81 /* 82 * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the 83 * interrupt `id`, 4 interrupts IDs at a time. 84 */ 85 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) 86 { 87 unsigned n = id >> IPRIORITYR_SHIFT; 88 mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); 89 } 90 91 /* 92 * Accessor to get the bit corresponding to interrupt ID 93 * from GIC Re-distributor IGROUPR0. 94 */ 95 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) 96 { 97 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 98 unsigned int reg_val = gicr_read_igroupr0(base); 99 100 return (reg_val >> bit_num) & 0x1; 101 } 102 103 /* 104 * Accessor to set the bit corresponding to interrupt ID 105 * in GIC Re-distributor IGROUPR0. 106 */ 107 void gicr_set_igroupr0(uintptr_t base, unsigned int id) 108 { 109 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 110 unsigned int reg_val = gicr_read_igroupr0(base); 111 112 gicr_write_igroupr0(base, reg_val | (1 << bit_num)); 113 } 114 115 /* 116 * Accessor to clear the bit corresponding to interrupt ID 117 * in GIC Re-distributor IGROUPR0. 118 */ 119 void gicr_clr_igroupr0(uintptr_t base, unsigned int id) 120 { 121 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 122 unsigned int reg_val = gicr_read_igroupr0(base); 123 124 gicr_write_igroupr0(base, reg_val & ~(1 << bit_num)); 125 } 126 127 /* 128 * Accessor to get the bit corresponding to interrupt ID 129 * from GIC Re-distributor IGRPMODR0. 130 */ 131 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) 132 { 133 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 134 unsigned int reg_val = gicr_read_igrpmodr0(base); 135 136 return (reg_val >> bit_num) & 0x1; 137 } 138 139 /* 140 * Accessor to set the bit corresponding to interrupt ID 141 * in GIC Re-distributor IGRPMODR0. 142 */ 143 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) 144 { 145 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 146 unsigned int reg_val = gicr_read_igrpmodr0(base); 147 148 gicr_write_igrpmodr0(base, reg_val | (1 << bit_num)); 149 } 150 151 /* 152 * Accessor to clear the bit corresponding to interrupt ID 153 * in GIC Re-distributor IGRPMODR0. 154 */ 155 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) 156 { 157 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 158 unsigned int reg_val = gicr_read_igrpmodr0(base); 159 160 gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num)); 161 } 162 163 /* 164 * Accessor to set the bit corresponding to interrupt ID 165 * in GIC Re-distributor ISENABLER0. 166 */ 167 void gicr_set_isenabler0(uintptr_t base, unsigned int id) 168 { 169 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); 170 171 gicr_write_isenabler0(base, (1 << bit_num)); 172 } 173 174 /* 175 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 176 * ICENABLER0. 177 */ 178 void gicr_set_icenabler0(uintptr_t base, unsigned int id) 179 { 180 unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); 181 182 gicr_write_icenabler0(base, (1 << bit_num)); 183 } 184 185 /* 186 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 187 * ISACTIVER0. 188 */ 189 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id) 190 { 191 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); 192 unsigned int reg_val = gicr_read_isactiver0(base); 193 194 return (reg_val >> bit_num) & 0x1; 195 } 196 197 /* 198 * Accessor to set the byte corresponding to interrupt ID 199 * in GIC Re-distributor IPRIORITYR. 200 */ 201 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) 202 { 203 mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); 204 } 205 206 /****************************************************************************** 207 * This function marks the core as awake in the re-distributor and 208 * ensures that the interface is active. 209 *****************************************************************************/ 210 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 211 { 212 /* 213 * The WAKER_PS_BIT should be changed to 0 214 * only when WAKER_CA_BIT is 1. 215 */ 216 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); 217 218 /* Mark the connected core as awake */ 219 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 220 221 /* Wait till the WAKER_CA_BIT changes to 0 */ 222 while (gicr_read_waker(gicr_base) & WAKER_CA_BIT) 223 ; 224 } 225 226 227 /****************************************************************************** 228 * This function marks the core as asleep in the re-distributor and ensures 229 * that the interface is quiescent. 230 *****************************************************************************/ 231 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 232 { 233 /* Mark the connected core as asleep */ 234 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 235 236 /* Wait till the WAKER_CA_BIT changes to 1 */ 237 while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT)) 238 ; 239 } 240 241 242 /******************************************************************************* 243 * This function probes the Redistributor frames when the driver is initialised 244 * and saves their base addresses. These base addresses are used later to 245 * initialise each Redistributor interface. 246 ******************************************************************************/ 247 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 248 unsigned int rdistif_num, 249 uintptr_t gicr_base, 250 mpidr_hash_fn mpidr_to_core_pos) 251 { 252 u_register_t mpidr; 253 unsigned int proc_num; 254 unsigned long long typer_val; 255 uintptr_t rdistif_base = gicr_base; 256 257 assert(rdistif_base_addrs); 258 259 /* 260 * Iterate over the Redistributor frames. Store the base address of each 261 * frame in the platform provided array. Use the "Processor Number" 262 * field to index into the array if the platform has not provided a hash 263 * function to convert an MPIDR (obtained from the "Affinity Value" 264 * field into a linear index. 265 */ 266 do { 267 typer_val = gicr_read_typer(rdistif_base); 268 if (mpidr_to_core_pos) { 269 mpidr = mpidr_from_gicr_typer(typer_val); 270 proc_num = mpidr_to_core_pos(mpidr); 271 } else { 272 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 273 TYPER_PROC_NUM_MASK; 274 } 275 assert(proc_num < rdistif_num); 276 rdistif_base_addrs[proc_num] = rdistif_base; 277 rdistif_base += (1 << GICR_PCPUBASE_SHIFT); 278 } while (!(typer_val & TYPER_LAST_BIT)); 279 } 280 281 /******************************************************************************* 282 * Helper function to configure the default attributes of SPIs. 283 ******************************************************************************/ 284 void gicv3_spis_configure_defaults(uintptr_t gicd_base) 285 { 286 unsigned int index, num_ints; 287 288 num_ints = gicd_read_typer(gicd_base); 289 num_ints &= TYPER_IT_LINES_NO_MASK; 290 num_ints = (num_ints + 1) << 5; 291 292 /* 293 * Treat all SPIs as G1NS by default. The number of interrupts is 294 * calculated as 32 * (IT_LINES + 1). We do 32 at a time. 295 */ 296 for (index = MIN_SPI_ID; index < num_ints; index += 32) 297 gicd_write_igroupr(gicd_base, index, ~0U); 298 299 /* Setup the default SPI priorities doing four at a time */ 300 for (index = MIN_SPI_ID; index < num_ints; index += 4) 301 gicd_write_ipriorityr(gicd_base, 302 index, 303 GICD_IPRIORITYR_DEF_VAL); 304 305 /* 306 * Treat all SPIs as level triggered by default, write 16 at 307 * a time 308 */ 309 for (index = MIN_SPI_ID; index < num_ints; index += 16) 310 gicd_write_icfgr(gicd_base, index, 0); 311 } 312 313 /******************************************************************************* 314 * Helper function to configure secure G0 and G1S SPIs. 315 ******************************************************************************/ 316 void gicv3_secure_spis_configure(uintptr_t gicd_base, 317 unsigned int num_ints, 318 const unsigned int *sec_intr_list, 319 unsigned int int_grp) 320 { 321 unsigned int index, irq_num; 322 unsigned long long gic_affinity_val; 323 324 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 325 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 326 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 327 328 for (index = 0; index < num_ints; index++) { 329 irq_num = sec_intr_list[index]; 330 if (irq_num >= MIN_SPI_ID) { 331 332 /* Configure this interrupt as a secure interrupt */ 333 gicd_clr_igroupr(gicd_base, irq_num); 334 335 /* Configure this interrupt as G0 or a G1S interrupt */ 336 if (int_grp == INTR_GROUP1S) 337 gicd_set_igrpmodr(gicd_base, irq_num); 338 else 339 gicd_clr_igrpmodr(gicd_base, irq_num); 340 341 /* Set the priority of this interrupt */ 342 gicd_set_ipriorityr(gicd_base, 343 irq_num, 344 GIC_HIGHEST_SEC_PRIORITY); 345 346 /* Target SPIs to the primary CPU */ 347 gic_affinity_val = 348 gicd_irouter_val_from_mpidr(read_mpidr(), 0); 349 gicd_write_irouter(gicd_base, 350 irq_num, 351 gic_affinity_val); 352 353 /* Enable this interrupt */ 354 gicd_set_isenabler(gicd_base, irq_num); 355 } 356 } 357 358 } 359 360 /******************************************************************************* 361 * Helper function to configure the default attributes of SPIs. 362 ******************************************************************************/ 363 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base) 364 { 365 unsigned int index; 366 367 /* 368 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 369 * more scalable approach as it avoids clearing the enable bits in the 370 * GICD_CTLR 371 */ 372 gicr_write_icenabler0(gicr_base, ~0); 373 gicr_wait_for_pending_write(gicr_base); 374 375 /* Treat all SGIs/PPIs as G1NS by default. */ 376 gicr_write_igroupr0(gicr_base, ~0U); 377 378 /* Setup the default PPI/SGI priorities doing four at a time */ 379 for (index = 0; index < MIN_SPI_ID; index += 4) 380 gicr_write_ipriorityr(gicr_base, 381 index, 382 GICD_IPRIORITYR_DEF_VAL); 383 384 /* Configure all PPIs as level triggered by default */ 385 gicr_write_icfgr1(gicr_base, 0); 386 } 387 388 /******************************************************************************* 389 * Helper function to configure secure G0 and G1S SPIs. 390 ******************************************************************************/ 391 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 392 unsigned int num_ints, 393 const unsigned int *sec_intr_list, 394 unsigned int int_grp) 395 { 396 unsigned int index, irq_num; 397 398 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 399 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 400 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 401 402 for (index = 0; index < num_ints; index++) { 403 irq_num = sec_intr_list[index]; 404 if (irq_num < MIN_SPI_ID) { 405 406 /* Configure this interrupt as a secure interrupt */ 407 gicr_clr_igroupr0(gicr_base, irq_num); 408 409 /* Configure this interrupt as G0 or a G1S interrupt */ 410 if (int_grp == INTR_GROUP1S) 411 gicr_set_igrpmodr0(gicr_base, irq_num); 412 else 413 gicr_clr_igrpmodr0(gicr_base, irq_num); 414 415 /* Set the priority of this interrupt */ 416 gicr_set_ipriorityr(gicr_base, 417 irq_num, 418 GIC_HIGHEST_SEC_PRIORITY); 419 420 /* Enable this interrupt */ 421 gicr_set_isenabler0(gicr_base, irq_num); 422 } 423 } 424 } 425