1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gic_common.h> 12 #include "../common/gic_common_private.h" 13 #include "gicv3_private.h" 14 15 /* 16 * Accessor to read the GIC Distributor IGRPMODR corresponding to the 17 * interrupt `id`, 32 interrupt IDs at a time. 18 */ 19 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) 20 { 21 unsigned n = id >> IGRPMODR_SHIFT; 22 return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); 23 } 24 25 /* 26 * Accessor to write the GIC Distributor IGRPMODR corresponding to the 27 * interrupt `id`, 32 interrupt IDs at a time. 28 */ 29 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) 30 { 31 unsigned n = id >> IGRPMODR_SHIFT; 32 mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); 33 } 34 35 /* 36 * Accessor to get the bit corresponding to interrupt ID 37 * in GIC Distributor IGRPMODR. 38 */ 39 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) 40 { 41 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 42 unsigned int reg_val = gicd_read_igrpmodr(base, id); 43 44 return (reg_val >> bit_num) & 0x1; 45 } 46 47 /* 48 * Accessor to set the bit corresponding to interrupt ID 49 * in GIC Distributor IGRPMODR. 50 */ 51 void gicd_set_igrpmodr(uintptr_t base, unsigned int id) 52 { 53 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 54 unsigned int reg_val = gicd_read_igrpmodr(base, id); 55 56 gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num)); 57 } 58 59 /* 60 * Accessor to clear the bit corresponding to interrupt ID 61 * in GIC Distributor IGRPMODR. 62 */ 63 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) 64 { 65 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 66 unsigned int reg_val = gicd_read_igrpmodr(base, id); 67 68 gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num)); 69 } 70 71 /* 72 * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the 73 * interrupt `id`, 4 interrupts IDs at a time. 74 */ 75 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) 76 { 77 unsigned n = id >> IPRIORITYR_SHIFT; 78 return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); 79 } 80 81 /* 82 * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the 83 * interrupt `id`, 4 interrupts IDs at a time. 84 */ 85 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) 86 { 87 unsigned n = id >> IPRIORITYR_SHIFT; 88 mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); 89 } 90 91 /* 92 * Accessor to get the bit corresponding to interrupt ID 93 * from GIC Re-distributor IGROUPR0. 94 */ 95 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) 96 { 97 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 98 unsigned int reg_val = gicr_read_igroupr0(base); 99 100 return (reg_val >> bit_num) & 0x1; 101 } 102 103 /* 104 * Accessor to set the bit corresponding to interrupt ID 105 * in GIC Re-distributor IGROUPR0. 106 */ 107 void gicr_set_igroupr0(uintptr_t base, unsigned int id) 108 { 109 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 110 unsigned int reg_val = gicr_read_igroupr0(base); 111 112 gicr_write_igroupr0(base, reg_val | (1 << bit_num)); 113 } 114 115 /* 116 * Accessor to clear the bit corresponding to interrupt ID 117 * in GIC Re-distributor IGROUPR0. 118 */ 119 void gicr_clr_igroupr0(uintptr_t base, unsigned int id) 120 { 121 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); 122 unsigned int reg_val = gicr_read_igroupr0(base); 123 124 gicr_write_igroupr0(base, reg_val & ~(1 << bit_num)); 125 } 126 127 /* 128 * Accessor to get the bit corresponding to interrupt ID 129 * from GIC Re-distributor IGRPMODR0. 130 */ 131 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) 132 { 133 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 134 unsigned int reg_val = gicr_read_igrpmodr0(base); 135 136 return (reg_val >> bit_num) & 0x1; 137 } 138 139 /* 140 * Accessor to set the bit corresponding to interrupt ID 141 * in GIC Re-distributor IGRPMODR0. 142 */ 143 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) 144 { 145 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 146 unsigned int reg_val = gicr_read_igrpmodr0(base); 147 148 gicr_write_igrpmodr0(base, reg_val | (1 << bit_num)); 149 } 150 151 /* 152 * Accessor to clear the bit corresponding to interrupt ID 153 * in GIC Re-distributor IGRPMODR0. 154 */ 155 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) 156 { 157 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); 158 unsigned int reg_val = gicr_read_igrpmodr0(base); 159 160 gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num)); 161 } 162 163 /* 164 * Accessor to set the bit corresponding to interrupt ID 165 * in GIC Re-distributor ISENABLER0. 166 */ 167 void gicr_set_isenabler0(uintptr_t base, unsigned int id) 168 { 169 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); 170 171 gicr_write_isenabler0(base, (1 << bit_num)); 172 } 173 174 /* 175 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 176 * ICENABLER0. 177 */ 178 void gicr_set_icenabler0(uintptr_t base, unsigned int id) 179 { 180 unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); 181 182 gicr_write_icenabler0(base, (1 << bit_num)); 183 } 184 185 /* 186 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 187 * ISACTIVER0. 188 */ 189 unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id) 190 { 191 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); 192 unsigned int reg_val = gicr_read_isactiver0(base); 193 194 return (reg_val >> bit_num) & 0x1; 195 } 196 197 /* 198 * Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor 199 * ICPENDRR0. 200 */ 201 void gicr_set_icpendr0(uintptr_t base, unsigned int id) 202 { 203 unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); 204 205 gicr_write_icpendr0(base, (1 << bit_num)); 206 } 207 208 /* 209 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor 210 * ISPENDR0. 211 */ 212 void gicr_set_ispendr0(uintptr_t base, unsigned int id) 213 { 214 unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); 215 216 gicr_write_ispendr0(base, (1 << bit_num)); 217 } 218 219 /* 220 * Accessor to set the byte corresponding to interrupt ID 221 * in GIC Re-distributor IPRIORITYR. 222 */ 223 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) 224 { 225 mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); 226 } 227 228 /****************************************************************************** 229 * This function marks the core as awake in the re-distributor and 230 * ensures that the interface is active. 231 *****************************************************************************/ 232 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) 233 { 234 /* 235 * The WAKER_PS_BIT should be changed to 0 236 * only when WAKER_CA_BIT is 1. 237 */ 238 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); 239 240 /* Mark the connected core as awake */ 241 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); 242 243 /* Wait till the WAKER_CA_BIT changes to 0 */ 244 while (gicr_read_waker(gicr_base) & WAKER_CA_BIT) 245 ; 246 } 247 248 249 /****************************************************************************** 250 * This function marks the core as asleep in the re-distributor and ensures 251 * that the interface is quiescent. 252 *****************************************************************************/ 253 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) 254 { 255 /* Mark the connected core as asleep */ 256 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); 257 258 /* Wait till the WAKER_CA_BIT changes to 1 */ 259 while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT)) 260 ; 261 } 262 263 264 /******************************************************************************* 265 * This function probes the Redistributor frames when the driver is initialised 266 * and saves their base addresses. These base addresses are used later to 267 * initialise each Redistributor interface. 268 ******************************************************************************/ 269 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 270 unsigned int rdistif_num, 271 uintptr_t gicr_base, 272 mpidr_hash_fn mpidr_to_core_pos) 273 { 274 u_register_t mpidr; 275 unsigned int proc_num; 276 unsigned long long typer_val; 277 uintptr_t rdistif_base = gicr_base; 278 279 assert(rdistif_base_addrs); 280 281 /* 282 * Iterate over the Redistributor frames. Store the base address of each 283 * frame in the platform provided array. Use the "Processor Number" 284 * field to index into the array if the platform has not provided a hash 285 * function to convert an MPIDR (obtained from the "Affinity Value" 286 * field into a linear index. 287 */ 288 do { 289 typer_val = gicr_read_typer(rdistif_base); 290 if (mpidr_to_core_pos) { 291 mpidr = mpidr_from_gicr_typer(typer_val); 292 proc_num = mpidr_to_core_pos(mpidr); 293 } else { 294 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & 295 TYPER_PROC_NUM_MASK; 296 } 297 assert(proc_num < rdistif_num); 298 rdistif_base_addrs[proc_num] = rdistif_base; 299 rdistif_base += (1 << GICR_PCPUBASE_SHIFT); 300 } while (!(typer_val & TYPER_LAST_BIT)); 301 } 302 303 /******************************************************************************* 304 * Helper function to configure the default attributes of SPIs. 305 ******************************************************************************/ 306 void gicv3_spis_configure_defaults(uintptr_t gicd_base) 307 { 308 unsigned int index, num_ints; 309 310 num_ints = gicd_read_typer(gicd_base); 311 num_ints &= TYPER_IT_LINES_NO_MASK; 312 num_ints = (num_ints + 1) << 5; 313 314 /* 315 * Treat all SPIs as G1NS by default. The number of interrupts is 316 * calculated as 32 * (IT_LINES + 1). We do 32 at a time. 317 */ 318 for (index = MIN_SPI_ID; index < num_ints; index += 32) 319 gicd_write_igroupr(gicd_base, index, ~0U); 320 321 /* Setup the default SPI priorities doing four at a time */ 322 for (index = MIN_SPI_ID; index < num_ints; index += 4) 323 gicd_write_ipriorityr(gicd_base, 324 index, 325 GICD_IPRIORITYR_DEF_VAL); 326 327 /* 328 * Treat all SPIs as level triggered by default, write 16 at 329 * a time 330 */ 331 for (index = MIN_SPI_ID; index < num_ints; index += 16) 332 gicd_write_icfgr(gicd_base, index, 0); 333 } 334 335 /******************************************************************************* 336 * Helper function to configure secure G0 and G1S SPIs. 337 ******************************************************************************/ 338 void gicv3_secure_spis_configure(uintptr_t gicd_base, 339 unsigned int num_ints, 340 const unsigned int *sec_intr_list, 341 unsigned int int_grp) 342 { 343 unsigned int index, irq_num; 344 unsigned long long gic_affinity_val; 345 346 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 347 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 348 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 349 350 for (index = 0; index < num_ints; index++) { 351 irq_num = sec_intr_list[index]; 352 if (irq_num >= MIN_SPI_ID) { 353 354 /* Configure this interrupt as a secure interrupt */ 355 gicd_clr_igroupr(gicd_base, irq_num); 356 357 /* Configure this interrupt as G0 or a G1S interrupt */ 358 if (int_grp == INTR_GROUP1S) 359 gicd_set_igrpmodr(gicd_base, irq_num); 360 else 361 gicd_clr_igrpmodr(gicd_base, irq_num); 362 363 /* Set the priority of this interrupt */ 364 gicd_set_ipriorityr(gicd_base, 365 irq_num, 366 GIC_HIGHEST_SEC_PRIORITY); 367 368 /* Target SPIs to the primary CPU */ 369 gic_affinity_val = 370 gicd_irouter_val_from_mpidr(read_mpidr(), 0); 371 gicd_write_irouter(gicd_base, 372 irq_num, 373 gic_affinity_val); 374 375 /* Enable this interrupt */ 376 gicd_set_isenabler(gicd_base, irq_num); 377 } 378 } 379 380 } 381 382 /******************************************************************************* 383 * Helper function to configure the default attributes of SPIs. 384 ******************************************************************************/ 385 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base) 386 { 387 unsigned int index; 388 389 /* 390 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 391 * more scalable approach as it avoids clearing the enable bits in the 392 * GICD_CTLR 393 */ 394 gicr_write_icenabler0(gicr_base, ~0); 395 gicr_wait_for_pending_write(gicr_base); 396 397 /* Treat all SGIs/PPIs as G1NS by default. */ 398 gicr_write_igroupr0(gicr_base, ~0U); 399 400 /* Setup the default PPI/SGI priorities doing four at a time */ 401 for (index = 0; index < MIN_SPI_ID; index += 4) 402 gicr_write_ipriorityr(gicr_base, 403 index, 404 GICD_IPRIORITYR_DEF_VAL); 405 406 /* Configure all PPIs as level triggered by default */ 407 gicr_write_icfgr1(gicr_base, 0); 408 } 409 410 /******************************************************************************* 411 * Helper function to configure secure G0 and G1S SPIs. 412 ******************************************************************************/ 413 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 414 unsigned int num_ints, 415 const unsigned int *sec_intr_list, 416 unsigned int int_grp) 417 { 418 unsigned int index, irq_num; 419 420 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); 421 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ 422 assert(num_ints ? (uintptr_t)sec_intr_list : 1); 423 424 for (index = 0; index < num_ints; index++) { 425 irq_num = sec_intr_list[index]; 426 if (irq_num < MIN_SPI_ID) { 427 428 /* Configure this interrupt as a secure interrupt */ 429 gicr_clr_igroupr0(gicr_base, irq_num); 430 431 /* Configure this interrupt as G0 or a G1S interrupt */ 432 if (int_grp == INTR_GROUP1S) 433 gicr_set_igrpmodr0(gicr_base, irq_num); 434 else 435 gicr_clr_igrpmodr0(gicr_base, irq_num); 436 437 /* Set the priority of this interrupt */ 438 gicr_set_ipriorityr(gicr_base, 439 irq_num, 440 GIC_HIGHEST_SEC_PRIORITY); 441 442 /* Enable this interrupt */ 443 gicr_set_isenabler0(gicr_base, irq_num); 444 } 445 } 446 } 447