1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 31 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 32 (INTR_TYPE_NS == INTR_GROUP1NS) && 33 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 34 35 /* 36 * This function returns the highest priority pending interrupt at 37 * the Interrupt controller 38 */ 39 uint32_t plat_ic_get_pending_interrupt_id(void) 40 { 41 unsigned int irqnr; 42 43 assert(IS_IN_EL3()); 44 irqnr = gicv3_get_pending_interrupt_id(); 45 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 46 INTR_ID_UNAVAILABLE : irqnr; 47 } 48 49 /* 50 * This function returns the type of the highest priority pending interrupt 51 * at the Interrupt controller. In the case of GICv3, the Highest Priority 52 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 53 * the id of the pending interrupt. The type of interrupt depends upon the 54 * id value as follows. 55 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 56 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 57 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 58 * type. 59 * 4. All other interrupt id's are reported as EL3 interrupt. 60 */ 61 uint32_t plat_ic_get_pending_interrupt_type(void) 62 { 63 unsigned int irqnr; 64 65 assert(IS_IN_EL3()); 66 irqnr = gicv3_get_pending_interrupt_type(); 67 68 switch (irqnr) { 69 case PENDING_G1S_INTID: 70 return INTR_TYPE_S_EL1; 71 case PENDING_G1NS_INTID: 72 return INTR_TYPE_NS; 73 case GIC_SPURIOUS_INTERRUPT: 74 return INTR_TYPE_INVAL; 75 default: 76 return INTR_TYPE_EL3; 77 } 78 } 79 80 /* 81 * This function returns the highest priority pending interrupt at 82 * the Interrupt controller and indicates to the Interrupt controller 83 * that the interrupt processing has started. 84 */ 85 uint32_t plat_ic_acknowledge_interrupt(void) 86 { 87 assert(IS_IN_EL3()); 88 return gicv3_acknowledge_interrupt(); 89 } 90 91 /* 92 * This function returns the type of the interrupt `id`, depending on how 93 * the interrupt has been configured in the interrupt controller 94 */ 95 uint32_t plat_ic_get_interrupt_type(uint32_t id) 96 { 97 assert(IS_IN_EL3()); 98 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 99 } 100 101 /* 102 * This functions is used to indicate to the interrupt controller that 103 * the processing of the interrupt corresponding to the `id` has 104 * finished. 105 */ 106 void plat_ic_end_of_interrupt(uint32_t id) 107 { 108 assert(IS_IN_EL3()); 109 gicv3_end_of_interrupt(id); 110 } 111 112 /* 113 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 114 * The interrupt controller knows which pin/line it uses to signal a type of 115 * interrupt. It lets the interrupt management framework determine for a type of 116 * interrupt and security state, which line should be used in the SCR_EL3 to 117 * control its routing to EL3. The interrupt line is represented as the bit 118 * position of the IRQ or FIQ bit in the SCR_EL3. 119 */ 120 uint32_t plat_interrupt_type_to_line(uint32_t type, 121 uint32_t security_state) 122 { 123 assert(type == INTR_TYPE_S_EL1 || 124 type == INTR_TYPE_EL3 || 125 type == INTR_TYPE_NS); 126 127 assert(sec_state_is_valid(security_state)); 128 assert(IS_IN_EL3()); 129 130 switch (type) { 131 case INTR_TYPE_S_EL1: 132 /* 133 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 134 * and as FIQ in the NS-EL0/1/2 contexts 135 */ 136 if (security_state == SECURE) 137 return __builtin_ctz(SCR_IRQ_BIT); 138 else 139 return __builtin_ctz(SCR_FIQ_BIT); 140 case INTR_TYPE_NS: 141 /* 142 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 143 * contexts and as IRQ in the NS-EL0/1/2 contexts. 144 */ 145 if (security_state == SECURE) 146 return __builtin_ctz(SCR_FIQ_BIT); 147 else 148 return __builtin_ctz(SCR_IRQ_BIT); 149 default: 150 assert(0); 151 /* Fall through in the release build */ 152 case INTR_TYPE_EL3: 153 /* 154 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 155 * NS-EL0/1/2 contexts 156 */ 157 return __builtin_ctz(SCR_FIQ_BIT); 158 } 159 } 160 161 unsigned int plat_ic_get_running_priority(void) 162 { 163 return gicv3_get_running_priority(); 164 } 165 166 #endif 167 #ifdef IMAGE_BL32 168 169 #pragma weak plat_ic_get_pending_interrupt_id 170 #pragma weak plat_ic_acknowledge_interrupt 171 #pragma weak plat_ic_end_of_interrupt 172 173 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 174 #ifdef AARCH32 175 #define IS_IN_EL1() IS_IN_SECURE() 176 #endif 177 178 /* 179 * This function returns the highest priority pending interrupt at 180 * the Interrupt controller 181 */ 182 uint32_t plat_ic_get_pending_interrupt_id(void) 183 { 184 unsigned int irqnr; 185 186 assert(IS_IN_EL1()); 187 irqnr = gicv3_get_pending_interrupt_id_sel1(); 188 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 189 INTR_ID_UNAVAILABLE : irqnr; 190 } 191 192 /* 193 * This function returns the highest priority pending interrupt at 194 * the Interrupt controller and indicates to the Interrupt controller 195 * that the interrupt processing has started. 196 */ 197 uint32_t plat_ic_acknowledge_interrupt(void) 198 { 199 assert(IS_IN_EL1()); 200 return gicv3_acknowledge_interrupt_sel1(); 201 } 202 203 /* 204 * This functions is used to indicate to the interrupt controller that 205 * the processing of the interrupt corresponding to the `id` has 206 * finished. 207 */ 208 void plat_ic_end_of_interrupt(uint32_t id) 209 { 210 assert(IS_IN_EL1()); 211 gicv3_end_of_interrupt_sel1(id); 212 } 213 #endif 214