xref: /rk3399_ARM-atf/plat/common/plat_gicv2.c (revision eb68ea9b10c190c237216dee92166f9e7b2ce3d4)
1 /*
2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 #include <assert.h>
7 #include <gic_common.h>
8 #include <gicv2.h>
9 #include <interrupt_mgmt.h>
10 
11 /*
12  * The following platform GIC functions are weakly defined. They
13  * provide typical implementations that may be re-used by multiple
14  * platforms but may also be overridden by a platform if required.
15  */
16 #pragma weak plat_ic_get_pending_interrupt_id
17 #pragma weak plat_ic_get_pending_interrupt_type
18 #pragma weak plat_ic_acknowledge_interrupt
19 #pragma weak plat_ic_get_interrupt_type
20 #pragma weak plat_ic_end_of_interrupt
21 #pragma weak plat_interrupt_type_to_line
22 
23 #pragma weak plat_ic_get_running_priority
24 
25 /*
26  * This function returns the highest priority pending interrupt at
27  * the Interrupt controller
28  */
29 uint32_t plat_ic_get_pending_interrupt_id(void)
30 {
31 	unsigned int id;
32 
33 	id = gicv2_get_pending_interrupt_id();
34 	if (id == GIC_SPURIOUS_INTERRUPT)
35 		return INTR_ID_UNAVAILABLE;
36 
37 	return id;
38 }
39 
40 /*
41  * This function returns the type of the highest priority pending interrupt
42  * at the Interrupt controller. In the case of GICv2, the Highest Priority
43  * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of
44  * the pending interrupt. The type of interrupt depends upon the id value
45  * as follows.
46  *   1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt
47  *   2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt.
48  *   3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt
49  *           type.
50  */
51 uint32_t plat_ic_get_pending_interrupt_type(void)
52 {
53 	unsigned int id;
54 
55 	id = gicv2_get_pending_interrupt_type();
56 
57 	/* Assume that all secure interrupts are S-EL1 interrupts */
58 	if (id < PENDING_G1_INTID)
59 		return INTR_TYPE_S_EL1;
60 
61 	if (id == GIC_SPURIOUS_INTERRUPT)
62 		return INTR_TYPE_INVAL;
63 
64 	return INTR_TYPE_NS;
65 }
66 
67 /*
68  * This function returns the highest priority pending interrupt at
69  * the Interrupt controller and indicates to the Interrupt controller
70  * that the interrupt processing has started.
71  */
72 uint32_t plat_ic_acknowledge_interrupt(void)
73 {
74 	return gicv2_acknowledge_interrupt();
75 }
76 
77 /*
78  * This function returns the type of the interrupt `id`, depending on how
79  * the interrupt has been configured in the interrupt controller
80  */
81 uint32_t plat_ic_get_interrupt_type(uint32_t id)
82 {
83 	unsigned int type;
84 
85 	type = gicv2_get_interrupt_group(id);
86 
87 	/* Assume that all secure interrupts are S-EL1 interrupts */
88 	return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1;
89 }
90 
91 /*
92  * This functions is used to indicate to the interrupt controller that
93  * the processing of the interrupt corresponding to the `id` has
94  * finished.
95  */
96 void plat_ic_end_of_interrupt(uint32_t id)
97 {
98 	gicv2_end_of_interrupt(id);
99 }
100 
101 /*
102  * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
103  * The interrupt controller knows which pin/line it uses to signal a type of
104  * interrupt. It lets the interrupt management framework determine
105  * for a type of interrupt and security state, which line should be used in the
106  * SCR_EL3 to control its routing to EL3. The interrupt line is represented
107  * as the bit position of the IRQ or FIQ bit in the SCR_EL3.
108  */
109 uint32_t plat_interrupt_type_to_line(uint32_t type,
110 				uint32_t security_state)
111 {
112 	assert(type == INTR_TYPE_S_EL1 ||
113 		       type == INTR_TYPE_EL3 ||
114 		       type == INTR_TYPE_NS);
115 
116 	/* Non-secure interrupts are signaled on the IRQ line always */
117 	if (type == INTR_TYPE_NS)
118 		return __builtin_ctz(SCR_IRQ_BIT);
119 
120 	/*
121 	 * Secure interrupts are signaled using the IRQ line if the FIQ is
122 	 * not enabled else they are signaled using the FIQ line.
123 	 */
124 	return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) :
125 						__builtin_ctz(SCR_IRQ_BIT));
126 }
127 
128 unsigned int plat_ic_get_running_priority(void)
129 {
130 	return gicv2_get_running_priority();
131 }
132