1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include <spinlock.h> 13 #include "gicv3_private.h" 14 15 const gicv3_driver_data_t *gicv3_driver_data; 16 static unsigned int gicv2_compat; 17 18 /* 19 * Spinlock to guard registers needing read-modify-write. APIs protected by this 20 * spinlock are used either at boot time (when only a single CPU is active), or 21 * when the system is fully coherent. 22 */ 23 spinlock_t gic_lock; 24 25 /* 26 * Redistributor power operations are weakly bound so that they can be 27 * overridden 28 */ 29 #pragma weak gicv3_rdistif_off 30 #pragma weak gicv3_rdistif_on 31 32 33 /* Helper macros to save and restore GICD registers to and from the context */ 34 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 35 do { \ 36 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 37 int_id += (1 << REG##_SHIFT)) { \ 38 gicd_write_##reg(base, int_id, \ 39 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 40 } \ 41 } while (0) 42 43 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 44 do { \ 45 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 46 int_id += (1 << REG##_SHIFT)) { \ 47 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 48 gicd_read_##reg(base, int_id); \ 49 } \ 50 } while (0) 51 52 53 /******************************************************************************* 54 * This function initialises the ARM GICv3 driver in EL3 with provided platform 55 * inputs. 56 ******************************************************************************/ 57 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 58 { 59 unsigned int gic_version; 60 61 assert(plat_driver_data); 62 assert(plat_driver_data->gicd_base); 63 assert(plat_driver_data->gicr_base); 64 assert(plat_driver_data->rdistif_num); 65 assert(plat_driver_data->rdistif_base_addrs); 66 67 assert(IS_IN_EL3()); 68 69 /* 70 * The platform should provide a list of at least one type of 71 * interrupts 72 */ 73 assert(plat_driver_data->g0_interrupt_array || 74 plat_driver_data->g1s_interrupt_array); 75 76 /* 77 * If there are no interrupts of a particular type, then the number of 78 * interrupts of that type should be 0 and vice-versa. 79 */ 80 assert(plat_driver_data->g0_interrupt_array ? 81 plat_driver_data->g0_interrupt_num : 82 plat_driver_data->g0_interrupt_num == 0); 83 assert(plat_driver_data->g1s_interrupt_array ? 84 plat_driver_data->g1s_interrupt_num : 85 plat_driver_data->g1s_interrupt_num == 0); 86 87 /* Check for system register support */ 88 #ifdef AARCH32 89 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 90 #else 91 assert(read_id_aa64pfr0_el1() & 92 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 93 #endif /* AARCH32 */ 94 95 /* The GIC version should be 3.0 */ 96 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 97 gic_version >>= PIDR2_ARCH_REV_SHIFT; 98 gic_version &= PIDR2_ARCH_REV_MASK; 99 assert(gic_version == ARCH_REV_GICV3); 100 101 /* 102 * Find out whether the GIC supports the GICv2 compatibility mode. The 103 * ARE_S bit resets to 0 if supported 104 */ 105 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 106 gicv2_compat >>= CTLR_ARE_S_SHIFT; 107 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 108 109 /* 110 * Find the base address of each implemented Redistributor interface. 111 * The number of interfaces should be equal to the number of CPUs in the 112 * system. The memory for saving these addresses has to be allocated by 113 * the platform port 114 */ 115 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 116 plat_driver_data->rdistif_num, 117 plat_driver_data->gicr_base, 118 plat_driver_data->mpidr_to_core_pos); 119 120 gicv3_driver_data = plat_driver_data; 121 122 /* 123 * The GIC driver data is initialized by the primary CPU with caches 124 * enabled. When the secondary CPU boots up, it initializes the 125 * GICC/GICR interface with the caches disabled. Hence flush the 126 * driver data to ensure coherency. This is not required if the 127 * platform has HW_ASSISTED_COHERENCY enabled. 128 */ 129 #if !HW_ASSISTED_COHERENCY 130 flush_dcache_range((uintptr_t) &gicv3_driver_data, 131 sizeof(gicv3_driver_data)); 132 flush_dcache_range((uintptr_t) gicv3_driver_data, 133 sizeof(*gicv3_driver_data)); 134 #endif 135 136 INFO("GICv3 %s legacy support detected." 137 " ARM GICV3 driver initialized in EL3\n", 138 gicv2_compat ? "with" : "without"); 139 } 140 141 /******************************************************************************* 142 * This function initialises the GIC distributor interface based upon the data 143 * provided by the platform while initialising the driver. 144 ******************************************************************************/ 145 void gicv3_distif_init(void) 146 { 147 unsigned int bitmap = 0; 148 149 assert(gicv3_driver_data); 150 assert(gicv3_driver_data->gicd_base); 151 assert(gicv3_driver_data->g1s_interrupt_array || 152 gicv3_driver_data->g0_interrupt_array); 153 154 assert(IS_IN_EL3()); 155 156 /* 157 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 158 * the ARE_S bit. The Distributor might generate a system error 159 * otherwise. 160 */ 161 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 162 CTLR_ENABLE_G0_BIT | 163 CTLR_ENABLE_G1S_BIT | 164 CTLR_ENABLE_G1NS_BIT, 165 RWP_TRUE); 166 167 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 168 gicd_set_ctlr(gicv3_driver_data->gicd_base, 169 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 170 171 /* Set the default attribute of all SPIs */ 172 gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base); 173 174 /* Configure the G1S SPIs */ 175 if (gicv3_driver_data->g1s_interrupt_array) { 176 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 177 gicv3_driver_data->g1s_interrupt_num, 178 gicv3_driver_data->g1s_interrupt_array, 179 INTR_GROUP1S); 180 bitmap |= CTLR_ENABLE_G1S_BIT; 181 } 182 183 /* Configure the G0 SPIs */ 184 if (gicv3_driver_data->g0_interrupt_array) { 185 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 186 gicv3_driver_data->g0_interrupt_num, 187 gicv3_driver_data->g0_interrupt_array, 188 INTR_GROUP0); 189 bitmap |= CTLR_ENABLE_G0_BIT; 190 } 191 192 /* Enable the secure SPIs now that they have been configured */ 193 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 194 } 195 196 /******************************************************************************* 197 * This function initialises the GIC Redistributor interface of the calling CPU 198 * (identified by the 'proc_num' parameter) based upon the data provided by the 199 * platform while initialising the driver. 200 ******************************************************************************/ 201 void gicv3_rdistif_init(unsigned int proc_num) 202 { 203 uintptr_t gicr_base; 204 205 assert(gicv3_driver_data); 206 assert(proc_num < gicv3_driver_data->rdistif_num); 207 assert(gicv3_driver_data->rdistif_base_addrs); 208 assert(gicv3_driver_data->gicd_base); 209 assert(gicd_read_ctlr(gicv3_driver_data->gicd_base) & CTLR_ARE_S_BIT); 210 assert(gicv3_driver_data->g1s_interrupt_array || 211 gicv3_driver_data->g0_interrupt_array); 212 213 assert(IS_IN_EL3()); 214 215 /* Power on redistributor */ 216 gicv3_rdistif_on(proc_num); 217 218 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 219 220 /* Set the default attribute of all SGIs and PPIs */ 221 gicv3_ppi_sgi_configure_defaults(gicr_base); 222 223 /* Configure the G1S SGIs/PPIs */ 224 if (gicv3_driver_data->g1s_interrupt_array) { 225 gicv3_secure_ppi_sgi_configure(gicr_base, 226 gicv3_driver_data->g1s_interrupt_num, 227 gicv3_driver_data->g1s_interrupt_array, 228 INTR_GROUP1S); 229 } 230 231 /* Configure the G0 SGIs/PPIs */ 232 if (gicv3_driver_data->g0_interrupt_array) { 233 gicv3_secure_ppi_sgi_configure(gicr_base, 234 gicv3_driver_data->g0_interrupt_num, 235 gicv3_driver_data->g0_interrupt_array, 236 INTR_GROUP0); 237 } 238 } 239 240 /******************************************************************************* 241 * Functions to perform power operations on GIC Redistributor 242 ******************************************************************************/ 243 void gicv3_rdistif_off(unsigned int proc_num) 244 { 245 return; 246 } 247 248 void gicv3_rdistif_on(unsigned int proc_num) 249 { 250 return; 251 } 252 253 /******************************************************************************* 254 * This function enables the GIC CPU interface of the calling CPU using only 255 * system register accesses. 256 ******************************************************************************/ 257 void gicv3_cpuif_enable(unsigned int proc_num) 258 { 259 uintptr_t gicr_base; 260 unsigned int scr_el3; 261 unsigned int icc_sre_el3; 262 263 assert(gicv3_driver_data); 264 assert(proc_num < gicv3_driver_data->rdistif_num); 265 assert(gicv3_driver_data->rdistif_base_addrs); 266 assert(IS_IN_EL3()); 267 268 /* Mark the connected core as awake */ 269 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 270 gicv3_rdistif_mark_core_awake(gicr_base); 271 272 /* Disable the legacy interrupt bypass */ 273 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 274 275 /* 276 * Enable system register access for EL3 and allow lower exception 277 * levels to configure the same for themselves. If the legacy mode is 278 * not supported, the SRE bit is RAO/WI 279 */ 280 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 281 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 282 283 scr_el3 = read_scr_el3(); 284 285 /* 286 * Switch to NS state to write Non secure ICC_SRE_EL1 and 287 * ICC_SRE_EL2 registers. 288 */ 289 write_scr_el3(scr_el3 | SCR_NS_BIT); 290 isb(); 291 292 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 293 write_icc_sre_el1(ICC_SRE_SRE_BIT); 294 isb(); 295 296 /* Switch to secure state. */ 297 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 298 isb(); 299 300 /* Program the idle priority in the PMR */ 301 write_icc_pmr_el1(GIC_PRI_MASK); 302 303 /* Enable Group0 interrupts */ 304 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 305 306 /* Enable Group1 Secure interrupts */ 307 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 308 IGRPEN1_EL3_ENABLE_G1S_BIT); 309 310 /* Write the secure ICC_SRE_EL1 register */ 311 write_icc_sre_el1(ICC_SRE_SRE_BIT); 312 isb(); 313 } 314 315 /******************************************************************************* 316 * This function disables the GIC CPU interface of the calling CPU using 317 * only system register accesses. 318 ******************************************************************************/ 319 void gicv3_cpuif_disable(unsigned int proc_num) 320 { 321 uintptr_t gicr_base; 322 323 assert(gicv3_driver_data); 324 assert(proc_num < gicv3_driver_data->rdistif_num); 325 assert(gicv3_driver_data->rdistif_base_addrs); 326 327 assert(IS_IN_EL3()); 328 329 /* Disable legacy interrupt bypass */ 330 write_icc_sre_el3(read_icc_sre_el3() | 331 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 332 333 /* Disable Group0 interrupts */ 334 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 335 ~IGRPEN1_EL1_ENABLE_G0_BIT); 336 337 /* Disable Group1 Secure and Non-Secure interrupts */ 338 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 339 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 340 IGRPEN1_EL3_ENABLE_G1S_BIT)); 341 342 /* Synchronise accesses to group enable registers */ 343 isb(); 344 345 /* Mark the connected core as asleep */ 346 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 347 gicv3_rdistif_mark_core_asleep(gicr_base); 348 } 349 350 /******************************************************************************* 351 * This function returns the id of the highest priority pending interrupt at 352 * the GIC cpu interface. 353 ******************************************************************************/ 354 unsigned int gicv3_get_pending_interrupt_id(void) 355 { 356 unsigned int id; 357 358 assert(IS_IN_EL3()); 359 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 360 361 /* 362 * If the ID is special identifier corresponding to G1S or G1NS 363 * interrupt, then read the highest pending group 1 interrupt. 364 */ 365 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 366 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 367 368 return id; 369 } 370 371 /******************************************************************************* 372 * This function returns the type of the highest priority pending interrupt at 373 * the GIC cpu interface. The return values can be one of the following : 374 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 375 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 376 * 0 - 1019 : The interrupt type is secure Group 0. 377 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 378 * sufficient priority to be signaled 379 ******************************************************************************/ 380 unsigned int gicv3_get_pending_interrupt_type(void) 381 { 382 assert(IS_IN_EL3()); 383 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 384 } 385 386 /******************************************************************************* 387 * This function returns the type of the interrupt id depending upon the group 388 * this interrupt has been configured under by the interrupt controller i.e. 389 * group0 or group1 Secure / Non Secure. The return value can be one of the 390 * following : 391 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 392 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 393 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 394 * interrupt. 395 ******************************************************************************/ 396 unsigned int gicv3_get_interrupt_type(unsigned int id, 397 unsigned int proc_num) 398 { 399 unsigned int igroup, grpmodr; 400 uintptr_t gicr_base; 401 402 assert(IS_IN_EL3()); 403 assert(gicv3_driver_data); 404 405 /* Ensure the parameters are valid */ 406 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 407 assert(proc_num < gicv3_driver_data->rdistif_num); 408 409 /* All LPI interrupts are Group 1 non secure */ 410 if (id >= MIN_LPI_ID) 411 return INTR_GROUP1NS; 412 413 if (id < MIN_SPI_ID) { 414 assert(gicv3_driver_data->rdistif_base_addrs); 415 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 416 igroup = gicr_get_igroupr0(gicr_base, id); 417 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 418 } else { 419 assert(gicv3_driver_data->gicd_base); 420 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 421 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 422 } 423 424 /* 425 * If the IGROUP bit is set, then it is a Group 1 Non secure 426 * interrupt 427 */ 428 if (igroup) 429 return INTR_GROUP1NS; 430 431 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 432 if (grpmodr) 433 return INTR_GROUP1S; 434 435 /* Else it is a Group 0 Secure interrupt */ 436 return INTR_GROUP0; 437 } 438 439 /***************************************************************************** 440 * Function to save and disable the GIC ITS register context. The power 441 * management of GIC ITS is implementation-defined and this function doesn't 442 * save any memory structures required to support ITS. As the sequence to save 443 * this state is implementation defined, it should be executed in platform 444 * specific code. Calling this function alone and then powering down the GIC and 445 * ITS without implementing the aforementioned platform specific code will 446 * corrupt the ITS state. 447 * 448 * This function must be invoked after the GIC CPU interface is disabled. 449 *****************************************************************************/ 450 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx) 451 { 452 int i; 453 454 assert(gicv3_driver_data); 455 assert(IS_IN_EL3()); 456 assert(its_ctx); 457 assert(gits_base); 458 459 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 460 461 /* Disable the ITS */ 462 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 463 (~GITS_CTLR_ENABLED_BIT)); 464 465 /* Wait for quiescent state */ 466 gits_wait_for_quiescent_bit(gits_base); 467 468 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 469 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 470 471 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 472 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 473 } 474 475 /***************************************************************************** 476 * Function to restore the GIC ITS register context. The power 477 * management of GIC ITS is implementation defined and this function doesn't 478 * restore any memory structures required to support ITS. The assumption is 479 * that these structures are in memory and are retained during system suspend. 480 * 481 * This must be invoked before the GIC CPU interface is enabled. 482 *****************************************************************************/ 483 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx) 484 { 485 int i; 486 487 assert(gicv3_driver_data); 488 assert(IS_IN_EL3()); 489 assert(its_ctx); 490 assert(gits_base); 491 492 /* Assert that the GITS is disabled and quiescent */ 493 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0); 494 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0); 495 496 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 497 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 498 499 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++) 500 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 501 502 /* Restore the ITS CTLR but leave the ITS disabled */ 503 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & 504 (~GITS_CTLR_ENABLED_BIT)); 505 } 506 507 /***************************************************************************** 508 * Function to save the GIC Redistributor register context. This function 509 * must be invoked after CPU interface disable and prior to Distributor save. 510 *****************************************************************************/ 511 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 512 { 513 uintptr_t gicr_base; 514 unsigned int int_id; 515 516 assert(gicv3_driver_data); 517 assert(proc_num < gicv3_driver_data->rdistif_num); 518 assert(gicv3_driver_data->rdistif_base_addrs); 519 assert(IS_IN_EL3()); 520 assert(rdist_ctx); 521 522 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 523 524 /* 525 * Wait for any write to GICR_CTLR to complete before trying to save any 526 * state. 527 */ 528 gicr_wait_for_pending_write(gicr_base); 529 530 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 531 532 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 533 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 534 535 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 536 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 537 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 538 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 539 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 540 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 541 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 542 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 543 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 544 int_id += (1 << IPRIORITYR_SHIFT)) { 545 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 546 gicr_read_ipriorityr(gicr_base, int_id); 547 } 548 549 550 /* 551 * Call the pre-save hook that implements the IMP DEF sequence that may 552 * be required on some GIC implementations. As this may need to access 553 * the Redistributor registers, we pass it proc_num. 554 */ 555 gicv3_distif_pre_save(proc_num); 556 } 557 558 /***************************************************************************** 559 * Function to restore the GIC Redistributor register context. We disable 560 * LPI and per-cpu interrupts before we start restore of the Redistributor. 561 * This function must be invoked after Distributor restore but prior to 562 * CPU interface enable. The pending and active interrupts are restored 563 * after the interrupts are fully configured and enabled. 564 *****************************************************************************/ 565 void gicv3_rdistif_init_restore(unsigned int proc_num, 566 const gicv3_redist_ctx_t * const rdist_ctx) 567 { 568 uintptr_t gicr_base; 569 unsigned int int_id; 570 571 assert(gicv3_driver_data); 572 assert(proc_num < gicv3_driver_data->rdistif_num); 573 assert(gicv3_driver_data->rdistif_base_addrs); 574 assert(IS_IN_EL3()); 575 assert(rdist_ctx); 576 577 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 578 579 /* Power on redistributor */ 580 gicv3_rdistif_on(proc_num); 581 582 /* 583 * Call the post-restore hook that implements the IMP DEF sequence that 584 * may be required on some GIC implementations. As this may need to 585 * access the Redistributor registers, we pass it proc_num. 586 */ 587 gicv3_distif_post_restore(proc_num); 588 589 /* 590 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 591 * more scalable approach as it avoids clearing the enable bits in the 592 * GICD_CTLR 593 */ 594 gicr_write_icenabler0(gicr_base, ~0); 595 /* Wait for pending writes to GICR_ICENABLER */ 596 gicr_wait_for_pending_write(gicr_base); 597 598 /* 599 * Disable the LPIs to avoid unpredictable behavior when writing to 600 * GICR_PROPBASER and GICR_PENDBASER. 601 */ 602 gicr_write_ctlr(gicr_base, 603 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 604 605 /* Restore registers' content */ 606 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 607 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 608 609 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 610 611 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 612 int_id += (1 << IPRIORITYR_SHIFT)) { 613 gicr_write_ipriorityr(gicr_base, int_id, 614 rdist_ctx->gicr_ipriorityr[ 615 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 616 } 617 618 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 619 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 620 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 621 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 622 623 /* Restore after group and priorities are set */ 624 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 625 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 626 627 /* 628 * Wait for all writes to the Distributor to complete before enabling 629 * the SGI and PPIs. 630 */ 631 gicr_wait_for_upstream_pending_write(gicr_base); 632 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 633 634 /* 635 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 636 * the first write to GICR_CTLR was still in flight (this write only 637 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 638 * bit). 639 */ 640 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 641 gicr_wait_for_pending_write(gicr_base); 642 } 643 644 /***************************************************************************** 645 * Function to save the GIC Distributor register context. This function 646 * must be invoked after CPU interface disable and Redistributor save. 647 *****************************************************************************/ 648 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 649 { 650 unsigned int num_ints; 651 652 assert(gicv3_driver_data); 653 assert(gicv3_driver_data->gicd_base); 654 assert(IS_IN_EL3()); 655 assert(dist_ctx); 656 657 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 658 659 num_ints = gicd_read_typer(gicd_base); 660 num_ints &= TYPER_IT_LINES_NO_MASK; 661 num_ints = (num_ints + 1) << 5; 662 663 assert(num_ints <= MAX_SPI_ID + 1); 664 665 /* Wait for pending write to complete */ 666 gicd_wait_for_pending_write(gicd_base); 667 668 /* Save the GICD_CTLR */ 669 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 670 671 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 672 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 673 674 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 675 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 676 677 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 678 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 679 680 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 681 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 682 683 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 684 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 685 686 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 687 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 688 689 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 690 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 691 692 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 693 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 694 695 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 696 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 697 698 /* 699 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 700 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 701 * driver. 702 */ 703 } 704 705 /***************************************************************************** 706 * Function to restore the GIC Distributor register context. We disable G0, G1S 707 * and G1NS interrupt groups before we start restore of the Distributor. This 708 * function must be invoked prior to Redistributor restore and CPU interface 709 * enable. The pending and active interrupts are restored after the interrupts 710 * are fully configured and enabled. 711 *****************************************************************************/ 712 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 713 { 714 unsigned int num_ints = 0; 715 716 assert(gicv3_driver_data); 717 assert(gicv3_driver_data->gicd_base); 718 assert(IS_IN_EL3()); 719 assert(dist_ctx); 720 721 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 722 723 /* 724 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 725 * the ARE_S bit. The Distributor might generate a system error 726 * otherwise. 727 */ 728 gicd_clr_ctlr(gicd_base, 729 CTLR_ENABLE_G0_BIT | 730 CTLR_ENABLE_G1S_BIT | 731 CTLR_ENABLE_G1NS_BIT, 732 RWP_TRUE); 733 734 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 735 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 736 737 num_ints = gicd_read_typer(gicd_base); 738 num_ints &= TYPER_IT_LINES_NO_MASK; 739 num_ints = (num_ints + 1) << 5; 740 741 assert(num_ints <= MAX_SPI_ID + 1); 742 743 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 744 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 745 746 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 747 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 748 749 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 750 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 751 752 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 753 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 754 755 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 756 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 757 758 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 759 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 760 761 /* 762 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 763 * configured. 764 */ 765 766 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 767 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 768 769 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 770 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 771 772 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 773 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 774 775 /* Restore the GICD_CTLR */ 776 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 777 gicd_wait_for_pending_write(gicd_base); 778 779 } 780 781 /******************************************************************************* 782 * This function gets the priority of the interrupt the processor is currently 783 * servicing. 784 ******************************************************************************/ 785 unsigned int gicv3_get_running_priority(void) 786 { 787 return read_icc_rpr_el1(); 788 } 789 790 /******************************************************************************* 791 * This function checks if the interrupt identified by id is active (whether the 792 * state is either active, or active and pending). The proc_num is used if the 793 * interrupt is SGI or PPI and programs the corresponding Redistributor 794 * interface. 795 ******************************************************************************/ 796 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 797 { 798 unsigned int value; 799 800 assert(gicv3_driver_data); 801 assert(gicv3_driver_data->gicd_base); 802 assert(proc_num < gicv3_driver_data->rdistif_num); 803 assert(gicv3_driver_data->rdistif_base_addrs); 804 assert(id <= MAX_SPI_ID); 805 806 if (id < MIN_SPI_ID) { 807 /* For SGIs and PPIs */ 808 value = gicr_get_isactiver0( 809 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 810 } else { 811 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 812 } 813 814 return value; 815 } 816 817 /******************************************************************************* 818 * This function enables the interrupt identified by id. The proc_num 819 * is used if the interrupt is SGI or PPI, and programs the corresponding 820 * Redistributor interface. 821 ******************************************************************************/ 822 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 823 { 824 assert(gicv3_driver_data); 825 assert(gicv3_driver_data->gicd_base); 826 assert(proc_num < gicv3_driver_data->rdistif_num); 827 assert(gicv3_driver_data->rdistif_base_addrs); 828 assert(id <= MAX_SPI_ID); 829 830 /* 831 * Ensure that any shared variable updates depending on out of band 832 * interrupt trigger are observed before enabling interrupt. 833 */ 834 dsbishst(); 835 if (id < MIN_SPI_ID) { 836 /* For SGIs and PPIs */ 837 gicr_set_isenabler0( 838 gicv3_driver_data->rdistif_base_addrs[proc_num], 839 id); 840 } else { 841 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 842 } 843 } 844 845 /******************************************************************************* 846 * This function disables the interrupt identified by id. The proc_num 847 * is used if the interrupt is SGI or PPI, and programs the corresponding 848 * Redistributor interface. 849 ******************************************************************************/ 850 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 851 { 852 assert(gicv3_driver_data); 853 assert(gicv3_driver_data->gicd_base); 854 assert(proc_num < gicv3_driver_data->rdistif_num); 855 assert(gicv3_driver_data->rdistif_base_addrs); 856 assert(id <= MAX_SPI_ID); 857 858 /* 859 * Disable interrupt, and ensure that any shared variable updates 860 * depending on out of band interrupt trigger are observed afterwards. 861 */ 862 if (id < MIN_SPI_ID) { 863 /* For SGIs and PPIs */ 864 gicr_set_icenabler0( 865 gicv3_driver_data->rdistif_base_addrs[proc_num], 866 id); 867 868 /* Write to clear enable requires waiting for pending writes */ 869 gicr_wait_for_pending_write( 870 gicv3_driver_data->rdistif_base_addrs[proc_num]); 871 } else { 872 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 873 874 /* Write to clear enable requires waiting for pending writes */ 875 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 876 } 877 878 dsbishst(); 879 } 880 881 /******************************************************************************* 882 * This function sets the interrupt priority as supplied for the given interrupt 883 * id. 884 ******************************************************************************/ 885 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 886 unsigned int priority) 887 { 888 uintptr_t gicr_base; 889 890 assert(gicv3_driver_data); 891 assert(gicv3_driver_data->gicd_base); 892 assert(proc_num < gicv3_driver_data->rdistif_num); 893 assert(gicv3_driver_data->rdistif_base_addrs); 894 assert(id <= MAX_SPI_ID); 895 896 if (id < MIN_SPI_ID) { 897 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 898 gicr_set_ipriorityr(gicr_base, id, priority); 899 } else { 900 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 901 } 902 } 903 904 /******************************************************************************* 905 * This function assigns group for the interrupt identified by id. The proc_num 906 * is used if the interrupt is SGI or PPI, and programs the corresponding 907 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 908 ******************************************************************************/ 909 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 910 unsigned int type) 911 { 912 unsigned int igroup = 0, grpmod = 0; 913 uintptr_t gicr_base; 914 915 assert(gicv3_driver_data); 916 assert(gicv3_driver_data->gicd_base); 917 assert(proc_num < gicv3_driver_data->rdistif_num); 918 assert(gicv3_driver_data->rdistif_base_addrs); 919 920 switch (type) { 921 case INTR_GROUP1S: 922 igroup = 0; 923 grpmod = 1; 924 break; 925 case INTR_GROUP0: 926 igroup = 0; 927 grpmod = 0; 928 break; 929 case INTR_GROUP1NS: 930 igroup = 1; 931 grpmod = 0; 932 break; 933 default: 934 assert(0); 935 } 936 937 if (id < MIN_SPI_ID) { 938 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 939 if (igroup) 940 gicr_set_igroupr0(gicr_base, id); 941 else 942 gicr_clr_igroupr0(gicr_base, id); 943 944 if (grpmod) 945 gicr_set_igrpmodr0(gicr_base, id); 946 else 947 gicr_clr_igrpmodr0(gicr_base, id); 948 } else { 949 /* Serialize read-modify-write to Distributor registers */ 950 spin_lock(&gic_lock); 951 if (igroup) 952 gicd_set_igroupr(gicv3_driver_data->gicd_base, id); 953 else 954 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 955 956 if (grpmod) 957 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id); 958 else 959 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 960 spin_unlock(&gic_lock); 961 } 962 } 963