1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 #pragma weak plat_ic_is_spi 31 #pragma weak plat_ic_is_ppi 32 #pragma weak plat_ic_is_sgi 33 #pragma weak plat_ic_get_interrupt_active 34 #pragma weak plat_ic_enable_interrupt 35 #pragma weak plat_ic_disable_interrupt 36 #pragma weak plat_ic_set_interrupt_priority 37 38 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 39 (INTR_TYPE_NS == INTR_GROUP1NS) && 40 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 41 42 /* 43 * This function returns the highest priority pending interrupt at 44 * the Interrupt controller 45 */ 46 uint32_t plat_ic_get_pending_interrupt_id(void) 47 { 48 unsigned int irqnr; 49 50 assert(IS_IN_EL3()); 51 irqnr = gicv3_get_pending_interrupt_id(); 52 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 53 INTR_ID_UNAVAILABLE : irqnr; 54 } 55 56 /* 57 * This function returns the type of the highest priority pending interrupt 58 * at the Interrupt controller. In the case of GICv3, the Highest Priority 59 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 60 * the id of the pending interrupt. The type of interrupt depends upon the 61 * id value as follows. 62 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 63 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 64 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 65 * type. 66 * 4. All other interrupt id's are reported as EL3 interrupt. 67 */ 68 uint32_t plat_ic_get_pending_interrupt_type(void) 69 { 70 unsigned int irqnr; 71 72 assert(IS_IN_EL3()); 73 irqnr = gicv3_get_pending_interrupt_type(); 74 75 switch (irqnr) { 76 case PENDING_G1S_INTID: 77 return INTR_TYPE_S_EL1; 78 case PENDING_G1NS_INTID: 79 return INTR_TYPE_NS; 80 case GIC_SPURIOUS_INTERRUPT: 81 return INTR_TYPE_INVAL; 82 default: 83 return INTR_TYPE_EL3; 84 } 85 } 86 87 /* 88 * This function returns the highest priority pending interrupt at 89 * the Interrupt controller and indicates to the Interrupt controller 90 * that the interrupt processing has started. 91 */ 92 uint32_t plat_ic_acknowledge_interrupt(void) 93 { 94 assert(IS_IN_EL3()); 95 return gicv3_acknowledge_interrupt(); 96 } 97 98 /* 99 * This function returns the type of the interrupt `id`, depending on how 100 * the interrupt has been configured in the interrupt controller 101 */ 102 uint32_t plat_ic_get_interrupt_type(uint32_t id) 103 { 104 assert(IS_IN_EL3()); 105 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 106 } 107 108 /* 109 * This functions is used to indicate to the interrupt controller that 110 * the processing of the interrupt corresponding to the `id` has 111 * finished. 112 */ 113 void plat_ic_end_of_interrupt(uint32_t id) 114 { 115 assert(IS_IN_EL3()); 116 gicv3_end_of_interrupt(id); 117 } 118 119 /* 120 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 121 * The interrupt controller knows which pin/line it uses to signal a type of 122 * interrupt. It lets the interrupt management framework determine for a type of 123 * interrupt and security state, which line should be used in the SCR_EL3 to 124 * control its routing to EL3. The interrupt line is represented as the bit 125 * position of the IRQ or FIQ bit in the SCR_EL3. 126 */ 127 uint32_t plat_interrupt_type_to_line(uint32_t type, 128 uint32_t security_state) 129 { 130 assert(type == INTR_TYPE_S_EL1 || 131 type == INTR_TYPE_EL3 || 132 type == INTR_TYPE_NS); 133 134 assert(sec_state_is_valid(security_state)); 135 assert(IS_IN_EL3()); 136 137 switch (type) { 138 case INTR_TYPE_S_EL1: 139 /* 140 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 141 * and as FIQ in the NS-EL0/1/2 contexts 142 */ 143 if (security_state == SECURE) 144 return __builtin_ctz(SCR_IRQ_BIT); 145 else 146 return __builtin_ctz(SCR_FIQ_BIT); 147 case INTR_TYPE_NS: 148 /* 149 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 150 * contexts and as IRQ in the NS-EL0/1/2 contexts. 151 */ 152 if (security_state == SECURE) 153 return __builtin_ctz(SCR_FIQ_BIT); 154 else 155 return __builtin_ctz(SCR_IRQ_BIT); 156 default: 157 assert(0); 158 /* Fall through in the release build */ 159 case INTR_TYPE_EL3: 160 /* 161 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 162 * NS-EL0/1/2 contexts 163 */ 164 return __builtin_ctz(SCR_FIQ_BIT); 165 } 166 } 167 168 unsigned int plat_ic_get_running_priority(void) 169 { 170 return gicv3_get_running_priority(); 171 } 172 173 int plat_ic_is_spi(unsigned int id) 174 { 175 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 176 } 177 178 int plat_ic_is_ppi(unsigned int id) 179 { 180 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 181 } 182 183 int plat_ic_is_sgi(unsigned int id) 184 { 185 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 186 } 187 188 unsigned int plat_ic_get_interrupt_active(unsigned int id) 189 { 190 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 191 } 192 193 void plat_ic_enable_interrupt(unsigned int id) 194 { 195 gicv3_enable_interrupt(id, plat_my_core_pos()); 196 } 197 198 void plat_ic_disable_interrupt(unsigned int id) 199 { 200 gicv3_disable_interrupt(id, plat_my_core_pos()); 201 } 202 203 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 204 { 205 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 206 } 207 #endif 208 #ifdef IMAGE_BL32 209 210 #pragma weak plat_ic_get_pending_interrupt_id 211 #pragma weak plat_ic_acknowledge_interrupt 212 #pragma weak plat_ic_end_of_interrupt 213 214 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 215 #ifdef AARCH32 216 #define IS_IN_EL1() IS_IN_SECURE() 217 #endif 218 219 /* 220 * This function returns the highest priority pending interrupt at 221 * the Interrupt controller 222 */ 223 uint32_t plat_ic_get_pending_interrupt_id(void) 224 { 225 unsigned int irqnr; 226 227 assert(IS_IN_EL1()); 228 irqnr = gicv3_get_pending_interrupt_id_sel1(); 229 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 230 INTR_ID_UNAVAILABLE : irqnr; 231 } 232 233 /* 234 * This function returns the highest priority pending interrupt at 235 * the Interrupt controller and indicates to the Interrupt controller 236 * that the interrupt processing has started. 237 */ 238 uint32_t plat_ic_acknowledge_interrupt(void) 239 { 240 assert(IS_IN_EL1()); 241 return gicv3_acknowledge_interrupt_sel1(); 242 } 243 244 /* 245 * This functions is used to indicate to the interrupt controller that 246 * the processing of the interrupt corresponding to the `id` has 247 * finished. 248 */ 249 void plat_ic_end_of_interrupt(uint32_t id) 250 { 251 assert(IS_IN_EL1()); 252 gicv3_end_of_interrupt_sel1(id); 253 } 254 #endif 255