1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <gic_common.h> 8 #include <gicv2.h> 9 #include <interrupt_mgmt.h> 10 #include <platform.h> 11 12 /* 13 * The following platform GIC functions are weakly defined. They 14 * provide typical implementations that may be re-used by multiple 15 * platforms but may also be overridden by a platform if required. 16 */ 17 #pragma weak plat_ic_get_pending_interrupt_id 18 #pragma weak plat_ic_get_pending_interrupt_type 19 #pragma weak plat_ic_acknowledge_interrupt 20 #pragma weak plat_ic_get_interrupt_type 21 #pragma weak plat_ic_end_of_interrupt 22 #pragma weak plat_interrupt_type_to_line 23 24 #pragma weak plat_ic_get_running_priority 25 #pragma weak plat_ic_is_spi 26 #pragma weak plat_ic_is_ppi 27 #pragma weak plat_ic_is_sgi 28 #pragma weak plat_ic_get_interrupt_active 29 #pragma weak plat_ic_enable_interrupt 30 #pragma weak plat_ic_disable_interrupt 31 #pragma weak plat_ic_set_interrupt_priority 32 #pragma weak plat_ic_set_interrupt_type 33 #pragma weak plat_ic_raise_el3_sgi 34 35 /* 36 * This function returns the highest priority pending interrupt at 37 * the Interrupt controller 38 */ 39 uint32_t plat_ic_get_pending_interrupt_id(void) 40 { 41 unsigned int id; 42 43 id = gicv2_get_pending_interrupt_id(); 44 if (id == GIC_SPURIOUS_INTERRUPT) 45 return INTR_ID_UNAVAILABLE; 46 47 return id; 48 } 49 50 /* 51 * This function returns the type of the highest priority pending interrupt 52 * at the Interrupt controller. In the case of GICv2, the Highest Priority 53 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 54 * the pending interrupt. The type of interrupt depends upon the id value 55 * as follows. 56 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 57 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 58 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 59 * type. 60 */ 61 uint32_t plat_ic_get_pending_interrupt_type(void) 62 { 63 unsigned int id; 64 65 id = gicv2_get_pending_interrupt_type(); 66 67 /* Assume that all secure interrupts are S-EL1 interrupts */ 68 if (id < PENDING_G1_INTID) { 69 #if GICV2_G0_FOR_EL3 70 return INTR_TYPE_EL3; 71 #else 72 return INTR_TYPE_S_EL1; 73 #endif 74 } 75 76 if (id == GIC_SPURIOUS_INTERRUPT) 77 return INTR_TYPE_INVAL; 78 79 return INTR_TYPE_NS; 80 } 81 82 /* 83 * This function returns the highest priority pending interrupt at 84 * the Interrupt controller and indicates to the Interrupt controller 85 * that the interrupt processing has started. 86 */ 87 uint32_t plat_ic_acknowledge_interrupt(void) 88 { 89 return gicv2_acknowledge_interrupt(); 90 } 91 92 /* 93 * This function returns the type of the interrupt `id`, depending on how 94 * the interrupt has been configured in the interrupt controller 95 */ 96 uint32_t plat_ic_get_interrupt_type(uint32_t id) 97 { 98 unsigned int type; 99 100 type = gicv2_get_interrupt_group(id); 101 102 /* Assume that all secure interrupts are S-EL1 interrupts */ 103 return type == GICV2_INTR_GROUP1 ? INTR_TYPE_NS : 104 #if GICV2_G0_FOR_EL3 105 INTR_TYPE_EL3; 106 #else 107 INTR_TYPE_S_EL1; 108 #endif 109 } 110 111 /* 112 * This functions is used to indicate to the interrupt controller that 113 * the processing of the interrupt corresponding to the `id` has 114 * finished. 115 */ 116 void plat_ic_end_of_interrupt(uint32_t id) 117 { 118 gicv2_end_of_interrupt(id); 119 } 120 121 /* 122 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 123 * The interrupt controller knows which pin/line it uses to signal a type of 124 * interrupt. It lets the interrupt management framework determine 125 * for a type of interrupt and security state, which line should be used in the 126 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 127 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 128 */ 129 uint32_t plat_interrupt_type_to_line(uint32_t type, 130 uint32_t security_state) 131 { 132 assert(type == INTR_TYPE_S_EL1 || 133 type == INTR_TYPE_EL3 || 134 type == INTR_TYPE_NS); 135 136 /* Non-secure interrupts are signaled on the IRQ line always */ 137 if (type == INTR_TYPE_NS) 138 return __builtin_ctz(SCR_IRQ_BIT); 139 140 /* 141 * Secure interrupts are signaled using the IRQ line if the FIQ is 142 * not enabled else they are signaled using the FIQ line. 143 */ 144 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : 145 __builtin_ctz(SCR_IRQ_BIT)); 146 } 147 148 unsigned int plat_ic_get_running_priority(void) 149 { 150 return gicv2_get_running_priority(); 151 } 152 153 int plat_ic_is_spi(unsigned int id) 154 { 155 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 156 } 157 158 int plat_ic_is_ppi(unsigned int id) 159 { 160 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 161 } 162 163 int plat_ic_is_sgi(unsigned int id) 164 { 165 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 166 } 167 168 unsigned int plat_ic_get_interrupt_active(unsigned int id) 169 { 170 return gicv2_get_interrupt_active(id); 171 } 172 173 void plat_ic_enable_interrupt(unsigned int id) 174 { 175 gicv2_enable_interrupt(id); 176 } 177 178 void plat_ic_disable_interrupt(unsigned int id) 179 { 180 gicv2_disable_interrupt(id); 181 } 182 183 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 184 { 185 gicv2_set_interrupt_priority(id, priority); 186 } 187 188 int plat_ic_has_interrupt_type(unsigned int type) 189 { 190 switch (type) { 191 #if GICV2_G0_FOR_EL3 192 case INTR_TYPE_EL3: 193 #else 194 case INTR_TYPE_S_EL1: 195 #endif 196 case INTR_TYPE_NS: 197 return 1; 198 default: 199 return 0; 200 } 201 } 202 203 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 204 { 205 int gicv2_type = 0; 206 207 /* Map canonical interrupt type to GICv2 type */ 208 switch (type) { 209 #if GICV2_G0_FOR_EL3 210 case INTR_TYPE_EL3: 211 #else 212 case INTR_TYPE_S_EL1: 213 #endif 214 gicv2_type = GICV2_INTR_GROUP0; 215 break; 216 case INTR_TYPE_NS: 217 gicv2_type = GICV2_INTR_GROUP1; 218 break; 219 default: 220 assert(0); 221 } 222 223 gicv2_set_interrupt_type(id, gicv2_type); 224 } 225 226 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 227 { 228 #if GICV2_G0_FOR_EL3 229 int id; 230 231 /* Target must be a valid MPIDR in the system */ 232 id = plat_core_pos_by_mpidr(target); 233 assert(id >= 0); 234 235 /* Verify that this is a secure SGI */ 236 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 237 238 gicv2_raise_sgi(sgi_num, id); 239 #else 240 assert(0); 241 #endif 242 } 243