1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_PRIVATE_H__ 8 #define __GICV2_PRIVATE_H__ 9 10 #include <gicv2.h> 11 #include <mmio.h> 12 #include <stdint.h> 13 14 /******************************************************************************* 15 * Private function prototypes 16 ******************************************************************************/ 17 void gicv2_spis_configure_defaults(uintptr_t gicd_base); 18 void gicv2_secure_spis_configure(uintptr_t gicd_base, 19 unsigned int num_ints, 20 const unsigned int *sec_intr_list); 21 void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, 22 unsigned int num_ints, 23 const unsigned int *sec_intr_list); 24 unsigned int gicv2_get_cpuif_id(uintptr_t base); 25 26 /******************************************************************************* 27 * GIC Distributor interface accessors for reading entire registers 28 ******************************************************************************/ 29 static inline unsigned int gicd_read_pidr2(uintptr_t base) 30 { 31 return mmio_read_32(base + GICD_PIDR2_GICV2); 32 } 33 34 /******************************************************************************* 35 * GIC Distributor interface accessors for writing entire registers 36 ******************************************************************************/ 37 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) 38 { 39 mmio_write_32(base + GICD_SGIR, val); 40 } 41 42 /******************************************************************************* 43 * GIC CPU interface accessors for reading entire registers 44 ******************************************************************************/ 45 46 static inline unsigned int gicc_read_ctlr(uintptr_t base) 47 { 48 return mmio_read_32(base + GICC_CTLR); 49 } 50 51 static inline unsigned int gicc_read_pmr(uintptr_t base) 52 { 53 return mmio_read_32(base + GICC_PMR); 54 } 55 56 static inline unsigned int gicc_read_BPR(uintptr_t base) 57 { 58 return mmio_read_32(base + GICC_BPR); 59 } 60 61 static inline unsigned int gicc_read_IAR(uintptr_t base) 62 { 63 return mmio_read_32(base + GICC_IAR); 64 } 65 66 static inline unsigned int gicc_read_EOIR(uintptr_t base) 67 { 68 return mmio_read_32(base + GICC_EOIR); 69 } 70 71 static inline unsigned int gicc_read_hppir(uintptr_t base) 72 { 73 return mmio_read_32(base + GICC_HPPIR); 74 } 75 76 static inline unsigned int gicc_read_ahppir(uintptr_t base) 77 { 78 return mmio_read_32(base + GICC_AHPPIR); 79 } 80 81 static inline unsigned int gicc_read_dir(uintptr_t base) 82 { 83 return mmio_read_32(base + GICC_DIR); 84 } 85 86 static inline unsigned int gicc_read_iidr(uintptr_t base) 87 { 88 return mmio_read_32(base + GICC_IIDR); 89 } 90 91 static inline unsigned int gicc_read_rpr(uintptr_t base) 92 { 93 return mmio_read_32(base + GICC_RPR); 94 } 95 96 /******************************************************************************* 97 * GIC CPU interface accessors for writing entire registers 98 ******************************************************************************/ 99 100 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) 101 { 102 mmio_write_32(base + GICC_CTLR, val); 103 } 104 105 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) 106 { 107 mmio_write_32(base + GICC_PMR, val); 108 } 109 110 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) 111 { 112 mmio_write_32(base + GICC_BPR, val); 113 } 114 115 116 static inline void gicc_write_IAR(uintptr_t base, unsigned int val) 117 { 118 mmio_write_32(base + GICC_IAR, val); 119 } 120 121 static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) 122 { 123 mmio_write_32(base + GICC_EOIR, val); 124 } 125 126 static inline void gicc_write_hppir(uintptr_t base, unsigned int val) 127 { 128 mmio_write_32(base + GICC_HPPIR, val); 129 } 130 131 static inline void gicc_write_dir(uintptr_t base, unsigned int val) 132 { 133 mmio_write_32(base + GICC_DIR, val); 134 } 135 136 #endif /* __GICV2_PRIVATE_H__ */ 137