1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_H__ 8 #define __GICV3_H__ 9 10 #include "utils_def.h" 11 12 /******************************************************************************* 13 * GICv3 miscellaneous definitions 14 ******************************************************************************/ 15 /* Interrupt group definitions */ 16 #define INTR_GROUP1S 0 17 #define INTR_GROUP0 1 18 #define INTR_GROUP1NS 2 19 20 /* Interrupt IDs reported by the HPPIR and IAR registers */ 21 #define PENDING_G1S_INTID 1020 22 #define PENDING_G1NS_INTID 1021 23 24 /* Constant to categorize LPI interrupt */ 25 #define MIN_LPI_ID 8192 26 27 /* GICv3 can only target up to 16 PEs with SGI */ 28 #define GICV3_MAX_SGI_TARGETS 16 29 30 /******************************************************************************* 31 * GICv3 specific Distributor interface register offsets and constants. 32 ******************************************************************************/ 33 #define GICD_STATUSR 0x10 34 #define GICD_SETSPI_NSR 0x40 35 #define GICD_CLRSPI_NSR 0x48 36 #define GICD_SETSPI_SR 0x50 37 #define GICD_CLRSPI_SR 0x50 38 #define GICD_IGRPMODR 0xd00 39 /* 40 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and 41 * n >= 32, making the effective offset as 0x6100. 42 */ 43 #define GICD_IROUTER 0x6000 44 #define GICD_PIDR2_GICV3 0xffe8 45 46 #define IGRPMODR_SHIFT 5 47 48 /* GICD_CTLR bit definitions */ 49 #define CTLR_ENABLE_G1NS_SHIFT 1 50 #define CTLR_ENABLE_G1S_SHIFT 2 51 #define CTLR_ARE_S_SHIFT 4 52 #define CTLR_ARE_NS_SHIFT 5 53 #define CTLR_DS_SHIFT 6 54 #define CTLR_E1NWF_SHIFT 7 55 #define GICD_CTLR_RWP_SHIFT 31 56 57 #define CTLR_ENABLE_G1NS_MASK 0x1 58 #define CTLR_ENABLE_G1S_MASK 0x1 59 #define CTLR_ARE_S_MASK 0x1 60 #define CTLR_ARE_NS_MASK 0x1 61 #define CTLR_DS_MASK 0x1 62 #define CTLR_E1NWF_MASK 0x1 63 #define GICD_CTLR_RWP_MASK 0x1 64 65 #define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) 66 #define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) 67 #define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) 68 #define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) 69 #define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) 70 #define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) 71 #define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) 72 73 /* GICD_IROUTER shifts and masks */ 74 #define IROUTER_SHIFT 0 75 #define IROUTER_IRM_SHIFT 31 76 #define IROUTER_IRM_MASK 0x1 77 78 #define GICV3_IRM_PE 0 79 #define GICV3_IRM_ANY 1 80 81 #define NUM_OF_DIST_REGS 30 82 83 /******************************************************************************* 84 * GICv3 Re-distributor interface registers & constants 85 ******************************************************************************/ 86 #define GICR_PCPUBASE_SHIFT 0x11 87 #define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ 88 #define GICR_CTLR 0x0 89 #define GICR_TYPER 0x08 90 #define GICR_WAKER 0x14 91 #define GICR_PROPBASER 0x70 92 #define GICR_PENDBASER 0x78 93 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) 94 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) 95 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) 96 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + 0x200) 97 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + 0x280) 98 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + 0x300) 99 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + 0x380) 100 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) 101 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) 102 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) 103 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) 104 #define GICR_NSACR (GICR_SGIBASE_OFFSET + 0xe00) 105 106 /* GICR_CTLR bit definitions */ 107 #define GICR_CTLR_UWP_SHIFT 31 108 #define GICR_CTLR_UWP_MASK 0x1 109 #define GICR_CTLR_UWP_BIT (1U << GICR_CTLR_UWP_SHIFT) 110 #define GICR_CTLR_RWP_SHIFT 3 111 #define GICR_CTLR_RWP_MASK 0x1 112 #define GICR_CTLR_RWP_BIT (1U << GICR_CTLR_RWP_SHIFT) 113 #define GICR_CTLR_EN_LPIS_BIT (1U << 0) 114 115 /* GICR_WAKER bit definitions */ 116 #define WAKER_CA_SHIFT 2 117 #define WAKER_PS_SHIFT 1 118 119 #define WAKER_CA_MASK 0x1 120 #define WAKER_PS_MASK 0x1 121 122 #define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) 123 #define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) 124 125 /* GICR_TYPER bit definitions */ 126 #define TYPER_AFF_VAL_SHIFT 32 127 #define TYPER_PROC_NUM_SHIFT 8 128 #define TYPER_LAST_SHIFT 4 129 130 #define TYPER_AFF_VAL_MASK 0xffffffff 131 #define TYPER_PROC_NUM_MASK 0xffff 132 #define TYPER_LAST_MASK 0x1 133 134 #define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) 135 136 #define NUM_OF_REDIST_REGS 30 137 138 /******************************************************************************* 139 * GICv3 CPU interface registers & constants 140 ******************************************************************************/ 141 /* ICC_SRE bit definitions*/ 142 #define ICC_SRE_EN_BIT (1 << 3) 143 #define ICC_SRE_DIB_BIT (1 << 2) 144 #define ICC_SRE_DFB_BIT (1 << 1) 145 #define ICC_SRE_SRE_BIT (1 << 0) 146 147 /* ICC_IGRPEN1_EL3 bit definitions */ 148 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 149 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 150 151 #define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 152 #define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) 153 154 /* ICC_IGRPEN0_EL1 bit definitions */ 155 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 156 #define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) 157 158 /* ICC_HPPIR0_EL1 bit definitions */ 159 #define HPPIR0_EL1_INTID_SHIFT 0 160 #define HPPIR0_EL1_INTID_MASK 0xffffff 161 162 /* ICC_HPPIR1_EL1 bit definitions */ 163 #define HPPIR1_EL1_INTID_SHIFT 0 164 #define HPPIR1_EL1_INTID_MASK 0xffffff 165 166 /* ICC_IAR0_EL1 bit definitions */ 167 #define IAR0_EL1_INTID_SHIFT 0 168 #define IAR0_EL1_INTID_MASK 0xffffff 169 170 /* ICC_IAR1_EL1 bit definitions */ 171 #define IAR1_EL1_INTID_SHIFT 0 172 #define IAR1_EL1_INTID_MASK 0xffffff 173 174 /* ICC SGI macros */ 175 #define SGIR_TGT_MASK 0xffff 176 #define SGIR_AFF1_SHIFT 16 177 #define SGIR_INTID_SHIFT 24 178 #define SGIR_INTID_MASK 0xf 179 #define SGIR_AFF2_SHIFT 32 180 #define SGIR_IRM_SHIFT 40 181 #define SGIR_IRM_MASK 0x1 182 #define SGIR_AFF3_SHIFT 48 183 #define SGIR_AFF_MASK 0xf 184 185 #define SGIR_IRM_TO_AFF 0 186 187 #define GICV3_SGIR_VALUE(aff3, aff2, aff1, intid, irm, tgt) \ 188 ((((uint64_t) (aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \ 189 (((uint64_t) (irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \ 190 (((uint64_t) (aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \ 191 (((intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \ 192 (((aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \ 193 ((tgt) & SGIR_TGT_MASK)) 194 195 /***************************************************************************** 196 * GICv3 ITS registers and constants 197 *****************************************************************************/ 198 199 #define GITS_CTLR 0x0 200 #define GITS_IIDR 0x4 201 #define GITS_TYPER 0x8 202 #define GITS_CBASER 0x80 203 #define GITS_CWRITER 0x88 204 #define GITS_CREADR 0x90 205 #define GITS_BASER 0x100 206 207 /* GITS_CTLR bit definitions */ 208 #define GITS_CTLR_ENABLED_BIT 1 209 #define GITS_CTLR_QUIESCENT_SHIFT 31 210 #define GITS_CTLR_QUIESCENT_BIT (1U << GITS_CTLR_QUIESCENT_SHIFT) 211 212 #ifndef __ASSEMBLY__ 213 214 #include <gic_common.h> 215 #include <stdint.h> 216 #include <types.h> 217 #include <utils_def.h> 218 219 #define gicv3_is_intr_id_special_identifier(id) \ 220 (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) 221 222 /******************************************************************************* 223 * Helper GICv3 macros for SEL1 224 ******************************************************************************/ 225 #define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ 226 IAR1_EL1_INTID_MASK 227 #define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ 228 HPPIR1_EL1_INTID_MASK 229 #define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) 230 231 232 /******************************************************************************* 233 * Helper GICv3 macros for EL3 234 ******************************************************************************/ 235 #define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ 236 IAR0_EL1_INTID_MASK 237 #define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) 238 239 /* 240 * This macro returns the total number of GICD registers corresponding to 241 * the name. 242 */ 243 #define GICD_NUM_REGS(reg_name) \ 244 DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT)) 245 246 #define GICR_NUM_REGS(reg_name) \ 247 DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT)) 248 249 /******************************************************************************* 250 * This structure describes some of the implementation defined attributes of the 251 * GICv3 IP. It is used by the platform port to specify these attributes in order 252 * to initialise the GICV3 driver. The attributes are described below. 253 * 254 * 1. The 'gicd_base' field contains the base address of the Distributor 255 * interface programmer's view. 256 * 257 * 2. The 'gicr_base' field contains the base address of the Re-distributor 258 * interface programmer's view. 259 * 260 * 3. The 'g0_interrupt_array' field is a ponter to an array in which each 261 * entry corresponds to an ID of a Group 0 interrupt. 262 * 263 * 4. The 'g0_interrupt_num' field contains the number of entries in the 264 * 'g0_interrupt_array'. 265 * 266 * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each 267 * entry corresponds to an ID of a Group 1 interrupt. 268 * 269 * 6. The 'g1s_interrupt_num' field contains the number of entries in the 270 * 'g1s_interrupt_array'. 271 * 272 * 7. The 'rdistif_num' field contains the number of Redistributor interfaces 273 * the GIC implements. This is equal to the number of CPUs or CPU interfaces 274 * instantiated in the GIC. 275 * 276 * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry 277 * for storing the base address of the Redistributor interface frame of each 278 * CPU in the system. The size of the array = 'rdistif_num'. The base 279 * addresses are detected during driver initialisation. 280 * 281 * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the 282 * driver will use to convert an MPIDR value to a linear core index. This 283 * index will be used for accessing the 'rdistif_base_addrs' array. This is 284 * an optional field. A GICv3 implementation maps each MPIDR to a linear core 285 * index as well. This mapping can be found by reading the "Affinity Value" 286 * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 287 * "Processor Numbers" are suitable to index into an array to access core 288 * specific information. If this not the case, the platform port must provide 289 * a hash function. Otherwise, the "Processor Number" field will be used to 290 * access the array elements. 291 ******************************************************************************/ 292 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 293 294 typedef struct gicv3_driver_data { 295 uintptr_t gicd_base; 296 uintptr_t gicr_base; 297 unsigned int g0_interrupt_num; 298 unsigned int g1s_interrupt_num; 299 const unsigned int *g0_interrupt_array; 300 const unsigned int *g1s_interrupt_array; 301 unsigned int rdistif_num; 302 uintptr_t *rdistif_base_addrs; 303 mpidr_hash_fn mpidr_to_core_pos; 304 } gicv3_driver_data_t; 305 306 typedef struct gicv3_redist_ctx { 307 /* 64 bits registers */ 308 uint64_t gicr_propbaser; 309 uint64_t gicr_pendbaser; 310 311 /* 32 bits registers */ 312 uint32_t gicr_ctlr; 313 uint32_t gicr_igroupr0; 314 uint32_t gicr_isenabler0; 315 uint32_t gicr_ispendr0; 316 uint32_t gicr_isactiver0; 317 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)]; 318 uint32_t gicr_icfgr0; 319 uint32_t gicr_icfgr1; 320 uint32_t gicr_igrpmodr0; 321 uint32_t gicr_nsacr; 322 } gicv3_redist_ctx_t; 323 324 typedef struct gicv3_dist_ctx { 325 /* 64 bits registers */ 326 uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM]; 327 328 /* 32 bits registers */ 329 uint32_t gicd_ctlr; 330 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)]; 331 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)]; 332 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)]; 333 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)]; 334 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)]; 335 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)]; 336 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)]; 337 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)]; 338 } gicv3_dist_ctx_t; 339 340 typedef struct gicv3_its_ctx { 341 /* 64 bits registers */ 342 uint64_t gits_cbaser; 343 uint64_t gits_cwriter; 344 uint64_t gits_baser[8]; 345 346 /* 32 bits registers */ 347 uint32_t gits_ctlr; 348 } gicv3_its_ctx_t; 349 350 /******************************************************************************* 351 * GICv3 EL3 driver API 352 ******************************************************************************/ 353 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 354 void gicv3_distif_init(void); 355 void gicv3_rdistif_init(unsigned int proc_num); 356 void gicv3_rdistif_on(unsigned int proc_num); 357 void gicv3_rdistif_off(unsigned int proc_num); 358 void gicv3_cpuif_enable(unsigned int proc_num); 359 void gicv3_cpuif_disable(unsigned int proc_num); 360 unsigned int gicv3_get_pending_interrupt_type(void); 361 unsigned int gicv3_get_pending_interrupt_id(void); 362 unsigned int gicv3_get_interrupt_type(unsigned int id, 363 unsigned int proc_num); 364 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx); 365 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx); 366 /* 367 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if 368 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no 369 * implementation-defined sequence is needed at these steps, an empty function 370 * can be provided. 371 */ 372 void gicv3_distif_post_restore(unsigned int proc_num); 373 void gicv3_distif_pre_save(unsigned int proc_num); 374 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx); 375 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx); 376 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx); 377 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx); 378 379 unsigned int gicv3_get_running_priority(void); 380 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num); 381 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num); 382 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num); 383 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 384 unsigned int priority); 385 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 386 unsigned int group); 387 void gicv3_raise_secure_g0_sgi(int sgi_num, u_register_t target); 388 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, 389 u_register_t mpidr); 390 391 #endif /* __ASSEMBLY__ */ 392 #endif /* __GICV3_H__ */ 393