1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <gic_common.h> 8 #include <gicv2.h> 9 #include <interrupt_mgmt.h> 10 11 /* 12 * The following platform GIC functions are weakly defined. They 13 * provide typical implementations that may be re-used by multiple 14 * platforms but may also be overridden by a platform if required. 15 */ 16 #pragma weak plat_ic_get_pending_interrupt_id 17 #pragma weak plat_ic_get_pending_interrupt_type 18 #pragma weak plat_ic_acknowledge_interrupt 19 #pragma weak plat_ic_get_interrupt_type 20 #pragma weak plat_ic_end_of_interrupt 21 #pragma weak plat_interrupt_type_to_line 22 23 #pragma weak plat_ic_get_running_priority 24 #pragma weak plat_ic_is_spi 25 #pragma weak plat_ic_is_ppi 26 #pragma weak plat_ic_is_sgi 27 #pragma weak plat_ic_get_interrupt_active 28 #pragma weak plat_ic_enable_interrupt 29 #pragma weak plat_ic_disable_interrupt 30 #pragma weak plat_ic_set_interrupt_priority 31 32 /* 33 * This function returns the highest priority pending interrupt at 34 * the Interrupt controller 35 */ 36 uint32_t plat_ic_get_pending_interrupt_id(void) 37 { 38 unsigned int id; 39 40 id = gicv2_get_pending_interrupt_id(); 41 if (id == GIC_SPURIOUS_INTERRUPT) 42 return INTR_ID_UNAVAILABLE; 43 44 return id; 45 } 46 47 /* 48 * This function returns the type of the highest priority pending interrupt 49 * at the Interrupt controller. In the case of GICv2, the Highest Priority 50 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 51 * the pending interrupt. The type of interrupt depends upon the id value 52 * as follows. 53 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 54 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 55 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 56 * type. 57 */ 58 uint32_t plat_ic_get_pending_interrupt_type(void) 59 { 60 unsigned int id; 61 62 id = gicv2_get_pending_interrupt_type(); 63 64 /* Assume that all secure interrupts are S-EL1 interrupts */ 65 if (id < PENDING_G1_INTID) 66 return INTR_TYPE_S_EL1; 67 68 if (id == GIC_SPURIOUS_INTERRUPT) 69 return INTR_TYPE_INVAL; 70 71 return INTR_TYPE_NS; 72 } 73 74 /* 75 * This function returns the highest priority pending interrupt at 76 * the Interrupt controller and indicates to the Interrupt controller 77 * that the interrupt processing has started. 78 */ 79 uint32_t plat_ic_acknowledge_interrupt(void) 80 { 81 return gicv2_acknowledge_interrupt(); 82 } 83 84 /* 85 * This function returns the type of the interrupt `id`, depending on how 86 * the interrupt has been configured in the interrupt controller 87 */ 88 uint32_t plat_ic_get_interrupt_type(uint32_t id) 89 { 90 unsigned int type; 91 92 type = gicv2_get_interrupt_group(id); 93 94 /* Assume that all secure interrupts are S-EL1 interrupts */ 95 return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1; 96 } 97 98 /* 99 * This functions is used to indicate to the interrupt controller that 100 * the processing of the interrupt corresponding to the `id` has 101 * finished. 102 */ 103 void plat_ic_end_of_interrupt(uint32_t id) 104 { 105 gicv2_end_of_interrupt(id); 106 } 107 108 /* 109 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 110 * The interrupt controller knows which pin/line it uses to signal a type of 111 * interrupt. It lets the interrupt management framework determine 112 * for a type of interrupt and security state, which line should be used in the 113 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 114 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 115 */ 116 uint32_t plat_interrupt_type_to_line(uint32_t type, 117 uint32_t security_state) 118 { 119 assert(type == INTR_TYPE_S_EL1 || 120 type == INTR_TYPE_EL3 || 121 type == INTR_TYPE_NS); 122 123 /* Non-secure interrupts are signaled on the IRQ line always */ 124 if (type == INTR_TYPE_NS) 125 return __builtin_ctz(SCR_IRQ_BIT); 126 127 /* 128 * Secure interrupts are signaled using the IRQ line if the FIQ is 129 * not enabled else they are signaled using the FIQ line. 130 */ 131 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : 132 __builtin_ctz(SCR_IRQ_BIT)); 133 } 134 135 unsigned int plat_ic_get_running_priority(void) 136 { 137 return gicv2_get_running_priority(); 138 } 139 140 int plat_ic_is_spi(unsigned int id) 141 { 142 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 143 } 144 145 int plat_ic_is_ppi(unsigned int id) 146 { 147 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 148 } 149 150 int plat_ic_is_sgi(unsigned int id) 151 { 152 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 153 } 154 155 unsigned int plat_ic_get_interrupt_active(unsigned int id) 156 { 157 return gicv2_get_interrupt_active(id); 158 } 159 160 void plat_ic_enable_interrupt(unsigned int id) 161 { 162 gicv2_enable_interrupt(id); 163 } 164 165 void plat_ic_disable_interrupt(unsigned int id) 166 { 167 gicv2_disable_interrupt(id); 168 } 169 170 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 171 { 172 gicv2_set_interrupt_priority(id, priority); 173 } 174