1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 #pragma weak plat_ic_is_spi 31 #pragma weak plat_ic_is_ppi 32 #pragma weak plat_ic_is_sgi 33 #pragma weak plat_ic_get_interrupt_active 34 #pragma weak plat_ic_enable_interrupt 35 #pragma weak plat_ic_disable_interrupt 36 #pragma weak plat_ic_set_interrupt_priority 37 #pragma weak plat_ic_set_interrupt_type 38 #pragma weak plat_ic_raise_el3_sgi 39 #pragma weak plat_ic_set_spi_routing 40 41 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 42 (INTR_TYPE_NS == INTR_GROUP1NS) && 43 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 44 45 /* 46 * This function returns the highest priority pending interrupt at 47 * the Interrupt controller 48 */ 49 uint32_t plat_ic_get_pending_interrupt_id(void) 50 { 51 unsigned int irqnr; 52 53 assert(IS_IN_EL3()); 54 irqnr = gicv3_get_pending_interrupt_id(); 55 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 56 INTR_ID_UNAVAILABLE : irqnr; 57 } 58 59 /* 60 * This function returns the type of the highest priority pending interrupt 61 * at the Interrupt controller. In the case of GICv3, the Highest Priority 62 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 63 * the id of the pending interrupt. The type of interrupt depends upon the 64 * id value as follows. 65 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 66 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 67 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 68 * type. 69 * 4. All other interrupt id's are reported as EL3 interrupt. 70 */ 71 uint32_t plat_ic_get_pending_interrupt_type(void) 72 { 73 unsigned int irqnr; 74 75 assert(IS_IN_EL3()); 76 irqnr = gicv3_get_pending_interrupt_type(); 77 78 switch (irqnr) { 79 case PENDING_G1S_INTID: 80 return INTR_TYPE_S_EL1; 81 case PENDING_G1NS_INTID: 82 return INTR_TYPE_NS; 83 case GIC_SPURIOUS_INTERRUPT: 84 return INTR_TYPE_INVAL; 85 default: 86 return INTR_TYPE_EL3; 87 } 88 } 89 90 /* 91 * This function returns the highest priority pending interrupt at 92 * the Interrupt controller and indicates to the Interrupt controller 93 * that the interrupt processing has started. 94 */ 95 uint32_t plat_ic_acknowledge_interrupt(void) 96 { 97 assert(IS_IN_EL3()); 98 return gicv3_acknowledge_interrupt(); 99 } 100 101 /* 102 * This function returns the type of the interrupt `id`, depending on how 103 * the interrupt has been configured in the interrupt controller 104 */ 105 uint32_t plat_ic_get_interrupt_type(uint32_t id) 106 { 107 assert(IS_IN_EL3()); 108 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 109 } 110 111 /* 112 * This functions is used to indicate to the interrupt controller that 113 * the processing of the interrupt corresponding to the `id` has 114 * finished. 115 */ 116 void plat_ic_end_of_interrupt(uint32_t id) 117 { 118 assert(IS_IN_EL3()); 119 gicv3_end_of_interrupt(id); 120 } 121 122 /* 123 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 124 * The interrupt controller knows which pin/line it uses to signal a type of 125 * interrupt. It lets the interrupt management framework determine for a type of 126 * interrupt and security state, which line should be used in the SCR_EL3 to 127 * control its routing to EL3. The interrupt line is represented as the bit 128 * position of the IRQ or FIQ bit in the SCR_EL3. 129 */ 130 uint32_t plat_interrupt_type_to_line(uint32_t type, 131 uint32_t security_state) 132 { 133 assert(type == INTR_TYPE_S_EL1 || 134 type == INTR_TYPE_EL3 || 135 type == INTR_TYPE_NS); 136 137 assert(sec_state_is_valid(security_state)); 138 assert(IS_IN_EL3()); 139 140 switch (type) { 141 case INTR_TYPE_S_EL1: 142 /* 143 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 144 * and as FIQ in the NS-EL0/1/2 contexts 145 */ 146 if (security_state == SECURE) 147 return __builtin_ctz(SCR_IRQ_BIT); 148 else 149 return __builtin_ctz(SCR_FIQ_BIT); 150 case INTR_TYPE_NS: 151 /* 152 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 153 * contexts and as IRQ in the NS-EL0/1/2 contexts. 154 */ 155 if (security_state == SECURE) 156 return __builtin_ctz(SCR_FIQ_BIT); 157 else 158 return __builtin_ctz(SCR_IRQ_BIT); 159 default: 160 assert(0); 161 /* Fall through in the release build */ 162 case INTR_TYPE_EL3: 163 /* 164 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 165 * NS-EL0/1/2 contexts 166 */ 167 return __builtin_ctz(SCR_FIQ_BIT); 168 } 169 } 170 171 unsigned int plat_ic_get_running_priority(void) 172 { 173 return gicv3_get_running_priority(); 174 } 175 176 int plat_ic_is_spi(unsigned int id) 177 { 178 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 179 } 180 181 int plat_ic_is_ppi(unsigned int id) 182 { 183 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 184 } 185 186 int plat_ic_is_sgi(unsigned int id) 187 { 188 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 189 } 190 191 unsigned int plat_ic_get_interrupt_active(unsigned int id) 192 { 193 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 194 } 195 196 void plat_ic_enable_interrupt(unsigned int id) 197 { 198 gicv3_enable_interrupt(id, plat_my_core_pos()); 199 } 200 201 void plat_ic_disable_interrupt(unsigned int id) 202 { 203 gicv3_disable_interrupt(id, plat_my_core_pos()); 204 } 205 206 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 207 { 208 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 209 } 210 211 int plat_ic_has_interrupt_type(unsigned int type) 212 { 213 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || 214 (type == INTR_TYPE_NS)); 215 return 1; 216 } 217 218 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 219 { 220 gicv3_set_interrupt_type(id, plat_my_core_pos(), type); 221 } 222 223 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 224 { 225 /* Target must be a valid MPIDR in the system */ 226 assert(plat_core_pos_by_mpidr(target) >= 0); 227 228 /* Verify that this is a secure EL3 SGI */ 229 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 230 231 gicv3_raise_secure_g0_sgi(sgi_num, target); 232 } 233 234 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 235 u_register_t mpidr) 236 { 237 unsigned int irm = 0; 238 239 switch (routing_mode) { 240 case INTR_ROUTING_MODE_PE: 241 assert(plat_core_pos_by_mpidr(mpidr) >= 0); 242 irm = GICV3_IRM_PE; 243 break; 244 case INTR_ROUTING_MODE_ANY: 245 irm = GICV3_IRM_ANY; 246 break; 247 default: 248 assert(0); 249 } 250 251 gicv3_set_spi_routing(id, irm, mpidr); 252 } 253 #endif 254 #ifdef IMAGE_BL32 255 256 #pragma weak plat_ic_get_pending_interrupt_id 257 #pragma weak plat_ic_acknowledge_interrupt 258 #pragma weak plat_ic_end_of_interrupt 259 260 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 261 #ifdef AARCH32 262 #define IS_IN_EL1() IS_IN_SECURE() 263 #endif 264 265 /* 266 * This function returns the highest priority pending interrupt at 267 * the Interrupt controller 268 */ 269 uint32_t plat_ic_get_pending_interrupt_id(void) 270 { 271 unsigned int irqnr; 272 273 assert(IS_IN_EL1()); 274 irqnr = gicv3_get_pending_interrupt_id_sel1(); 275 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 276 INTR_ID_UNAVAILABLE : irqnr; 277 } 278 279 /* 280 * This function returns the highest priority pending interrupt at 281 * the Interrupt controller and indicates to the Interrupt controller 282 * that the interrupt processing has started. 283 */ 284 uint32_t plat_ic_acknowledge_interrupt(void) 285 { 286 assert(IS_IN_EL1()); 287 return gicv3_acknowledge_interrupt_sel1(); 288 } 289 290 /* 291 * This functions is used to indicate to the interrupt controller that 292 * the processing of the interrupt corresponding to the `id` has 293 * finished. 294 */ 295 void plat_ic_end_of_interrupt(uint32_t id) 296 { 297 assert(IS_IN_EL1()); 298 gicv3_end_of_interrupt_sel1(id); 299 } 300 #endif 301