1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <cassert.h> 10 #include <gic_common.h> 11 #include <gicv3.h> 12 #include <interrupt_mgmt.h> 13 #include <platform.h> 14 15 #ifdef IMAGE_BL31 16 17 /* 18 * The following platform GIC functions are weakly defined. They 19 * provide typical implementations that may be re-used by multiple 20 * platforms but may also be overridden by a platform if required. 21 */ 22 #pragma weak plat_ic_get_pending_interrupt_id 23 #pragma weak plat_ic_get_pending_interrupt_type 24 #pragma weak plat_ic_acknowledge_interrupt 25 #pragma weak plat_ic_get_interrupt_type 26 #pragma weak plat_ic_end_of_interrupt 27 #pragma weak plat_interrupt_type_to_line 28 29 #pragma weak plat_ic_get_running_priority 30 #pragma weak plat_ic_is_spi 31 #pragma weak plat_ic_is_ppi 32 #pragma weak plat_ic_is_sgi 33 #pragma weak plat_ic_get_interrupt_active 34 #pragma weak plat_ic_enable_interrupt 35 #pragma weak plat_ic_disable_interrupt 36 #pragma weak plat_ic_set_interrupt_priority 37 #pragma weak plat_ic_set_interrupt_type 38 #pragma weak plat_ic_raise_el3_sgi 39 40 CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && 41 (INTR_TYPE_NS == INTR_GROUP1NS) && 42 (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); 43 44 /* 45 * This function returns the highest priority pending interrupt at 46 * the Interrupt controller 47 */ 48 uint32_t plat_ic_get_pending_interrupt_id(void) 49 { 50 unsigned int irqnr; 51 52 assert(IS_IN_EL3()); 53 irqnr = gicv3_get_pending_interrupt_id(); 54 return (gicv3_is_intr_id_special_identifier(irqnr)) ? 55 INTR_ID_UNAVAILABLE : irqnr; 56 } 57 58 /* 59 * This function returns the type of the highest priority pending interrupt 60 * at the Interrupt controller. In the case of GICv3, the Highest Priority 61 * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine 62 * the id of the pending interrupt. The type of interrupt depends upon the 63 * id value as follows. 64 * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt 65 * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. 66 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 67 * type. 68 * 4. All other interrupt id's are reported as EL3 interrupt. 69 */ 70 uint32_t plat_ic_get_pending_interrupt_type(void) 71 { 72 unsigned int irqnr; 73 74 assert(IS_IN_EL3()); 75 irqnr = gicv3_get_pending_interrupt_type(); 76 77 switch (irqnr) { 78 case PENDING_G1S_INTID: 79 return INTR_TYPE_S_EL1; 80 case PENDING_G1NS_INTID: 81 return INTR_TYPE_NS; 82 case GIC_SPURIOUS_INTERRUPT: 83 return INTR_TYPE_INVAL; 84 default: 85 return INTR_TYPE_EL3; 86 } 87 } 88 89 /* 90 * This function returns the highest priority pending interrupt at 91 * the Interrupt controller and indicates to the Interrupt controller 92 * that the interrupt processing has started. 93 */ 94 uint32_t plat_ic_acknowledge_interrupt(void) 95 { 96 assert(IS_IN_EL3()); 97 return gicv3_acknowledge_interrupt(); 98 } 99 100 /* 101 * This function returns the type of the interrupt `id`, depending on how 102 * the interrupt has been configured in the interrupt controller 103 */ 104 uint32_t plat_ic_get_interrupt_type(uint32_t id) 105 { 106 assert(IS_IN_EL3()); 107 return gicv3_get_interrupt_type(id, plat_my_core_pos()); 108 } 109 110 /* 111 * This functions is used to indicate to the interrupt controller that 112 * the processing of the interrupt corresponding to the `id` has 113 * finished. 114 */ 115 void plat_ic_end_of_interrupt(uint32_t id) 116 { 117 assert(IS_IN_EL3()); 118 gicv3_end_of_interrupt(id); 119 } 120 121 /* 122 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 123 * The interrupt controller knows which pin/line it uses to signal a type of 124 * interrupt. It lets the interrupt management framework determine for a type of 125 * interrupt and security state, which line should be used in the SCR_EL3 to 126 * control its routing to EL3. The interrupt line is represented as the bit 127 * position of the IRQ or FIQ bit in the SCR_EL3. 128 */ 129 uint32_t plat_interrupt_type_to_line(uint32_t type, 130 uint32_t security_state) 131 { 132 assert(type == INTR_TYPE_S_EL1 || 133 type == INTR_TYPE_EL3 || 134 type == INTR_TYPE_NS); 135 136 assert(sec_state_is_valid(security_state)); 137 assert(IS_IN_EL3()); 138 139 switch (type) { 140 case INTR_TYPE_S_EL1: 141 /* 142 * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts 143 * and as FIQ in the NS-EL0/1/2 contexts 144 */ 145 if (security_state == SECURE) 146 return __builtin_ctz(SCR_IRQ_BIT); 147 else 148 return __builtin_ctz(SCR_FIQ_BIT); 149 case INTR_TYPE_NS: 150 /* 151 * The Non secure interrupts will be signaled as FIQ in S-EL0/1 152 * contexts and as IRQ in the NS-EL0/1/2 contexts. 153 */ 154 if (security_state == SECURE) 155 return __builtin_ctz(SCR_FIQ_BIT); 156 else 157 return __builtin_ctz(SCR_IRQ_BIT); 158 default: 159 assert(0); 160 /* Fall through in the release build */ 161 case INTR_TYPE_EL3: 162 /* 163 * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and 164 * NS-EL0/1/2 contexts 165 */ 166 return __builtin_ctz(SCR_FIQ_BIT); 167 } 168 } 169 170 unsigned int plat_ic_get_running_priority(void) 171 { 172 return gicv3_get_running_priority(); 173 } 174 175 int plat_ic_is_spi(unsigned int id) 176 { 177 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 178 } 179 180 int plat_ic_is_ppi(unsigned int id) 181 { 182 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 183 } 184 185 int plat_ic_is_sgi(unsigned int id) 186 { 187 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 188 } 189 190 unsigned int plat_ic_get_interrupt_active(unsigned int id) 191 { 192 return gicv3_get_interrupt_active(id, plat_my_core_pos()); 193 } 194 195 void plat_ic_enable_interrupt(unsigned int id) 196 { 197 gicv3_enable_interrupt(id, plat_my_core_pos()); 198 } 199 200 void plat_ic_disable_interrupt(unsigned int id) 201 { 202 gicv3_disable_interrupt(id, plat_my_core_pos()); 203 } 204 205 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 206 { 207 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); 208 } 209 210 int plat_ic_has_interrupt_type(unsigned int type) 211 { 212 assert((type == INTR_TYPE_EL3) || (type == INTR_TYPE_S_EL1) || 213 (type == INTR_TYPE_NS)); 214 return 1; 215 } 216 217 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 218 { 219 gicv3_set_interrupt_type(id, plat_my_core_pos(), type); 220 } 221 222 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 223 { 224 /* Target must be a valid MPIDR in the system */ 225 assert(plat_core_pos_by_mpidr(target) >= 0); 226 227 /* Verify that this is a secure EL3 SGI */ 228 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 229 230 gicv3_raise_secure_g0_sgi(sgi_num, target); 231 } 232 #endif 233 #ifdef IMAGE_BL32 234 235 #pragma weak plat_ic_get_pending_interrupt_id 236 #pragma weak plat_ic_acknowledge_interrupt 237 #pragma weak plat_ic_end_of_interrupt 238 239 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ 240 #ifdef AARCH32 241 #define IS_IN_EL1() IS_IN_SECURE() 242 #endif 243 244 /* 245 * This function returns the highest priority pending interrupt at 246 * the Interrupt controller 247 */ 248 uint32_t plat_ic_get_pending_interrupt_id(void) 249 { 250 unsigned int irqnr; 251 252 assert(IS_IN_EL1()); 253 irqnr = gicv3_get_pending_interrupt_id_sel1(); 254 return (irqnr == GIC_SPURIOUS_INTERRUPT) ? 255 INTR_ID_UNAVAILABLE : irqnr; 256 } 257 258 /* 259 * This function returns the highest priority pending interrupt at 260 * the Interrupt controller and indicates to the Interrupt controller 261 * that the interrupt processing has started. 262 */ 263 uint32_t plat_ic_acknowledge_interrupt(void) 264 { 265 assert(IS_IN_EL1()); 266 return gicv3_acknowledge_interrupt_sel1(); 267 } 268 269 /* 270 * This functions is used to indicate to the interrupt controller that 271 * the processing of the interrupt corresponding to the `id` has 272 * finished. 273 */ 274 void plat_ic_end_of_interrupt(uint32_t id) 275 { 276 assert(IS_IN_EL1()); 277 gicv3_end_of_interrupt_sel1(id); 278 } 279 #endif 280