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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-vop-clk-set.dtsi16 assigned-clocks = <&cru SCLK_EMMC>;
17 assigned-clock-parents = <&cru PLL_GPLL>;
22 assigned-clocks = <&cru SCLK_UART0_SRC>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
27 assigned-clocks = <&cru SCLK_UART_SRC>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
32 assigned-clocks = <&cru SCLK_UART_SRC>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
37 assigned-clocks = <&cru SCLK_UART_SRC>;
38 assigned-clock-parents = <&cru PLL_GPLL>;
[all …]
H A Drk3588.dtsi94 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
95 <&cru ACLK_USB3OTG1>;
107 resets = <&cru SRST_A_USB3OTG1>;
150 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
152 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
178 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
179 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
180 assigned-clock-parents = <&cru PLL_AUPLL>;
190 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
192 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
[all …]
H A Drk3588-vehicle-evb-image-reverse.dtsi45 clocks = <&cru ACLK_VICAP>,
46 <&cru HCLK_VICAP>,
47 <&cru DCLK_VICAP>;
51 resets = <&cru SRST_A_VICAP>,
52 <&cru SRST_H_VICAP>,
53 <&cru SRST_D_VICAP>;
57 assigned-clocks = <&cru DCLK_VICAP>;
63 rockchip,cru = <&cru>;
80 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>,
81 <&cru PCLK_MIPI_DCPHY0>,
[all …]
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c65 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() argument
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
143 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mac_set_clk() argument
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
168 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) in rv1108_sfc_set_clk() argument
[all …]
H A Dclk_rk3288.c235 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
239 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
269 static u32 rkclk_pll_get_rate(struct rk3288_cru *cru, in rkclk_pll_get_rate() argument
275 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
282 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
302 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, in rkclk_configure_ddr() argument
332 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
335 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
342 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
436 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) in rockchip_mac_set_clk() argument
[all …]
H A Dclk_rk1808.c97 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_get_clk() local
102 con = readl(&cru->pmu_clksel_con[7]); in rk1808_i2c_get_clk()
106 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
110 con = readl(&cru->clksel_con[59]); in rk1808_i2c_get_clk()
114 con = readl(&cru->clksel_con[60]); in rk1808_i2c_get_clk()
118 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
122 con = readl(&cru->clksel_con[71]); in rk1808_i2c_get_clk()
136 struct rk1808_cru *cru = priv->cru; in rk1808_i2c_set_clk() local
144 rk_clrsetreg(&cru->pmu_clksel_con[7], in rk1808_i2c_set_clk()
150 rk_clrsetreg(&cru->clksel_con[59], in rk1808_i2c_set_clk()
[all …]
H A Dclk_rk3328.c120 struct rk3328_cru *cru = priv->cru; in rk3328_armclk_set_clk() local
136 priv->cru, NPLL); in rk3328_armclk_set_clk()
139 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
141 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
145 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
150 rk_clrsetreg(&cru->clksel_con[1], in rk3328_armclk_set_clk()
154 rk_clrsetreg(&cru->clksel_con[0], in rk3328_armclk_set_clk()
159 priv->cru, NPLL, hz)) in rk3328_armclk_set_clk()
163 return rockchip_pll_get_rate(&rk3328_pll_clks[NPLL], priv->cru, NPLL); in rk3328_armclk_set_clk()
169 struct rk3328_cru *cru = priv->cru; in rk3328_i2c_get_clk() local
[all …]
H A Dclk_rk322x.c94 struct rk322x_cru *cru = priv->cru; in rk322x_armclk_set_clk() local
110 priv->cru, APLL); in rk322x_armclk_set_clk()
113 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
115 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
119 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
124 rk_clrsetreg(&cru->cru_clksel_con[1], in rk322x_armclk_set_clk()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rk322x_armclk_set_clk()
133 priv->cru, APLL, hz)) in rk322x_armclk_set_clk()
137 return rockchip_pll_get_rate(&rk322x_pll_clks[APLL], priv->cru, APLL); in rk322x_armclk_set_clk()
143 struct rk322x_cru *cru = priv->cru; in rk322x_mmc_get_clk() local
[all …]
H A Dclk_rk3308.c139 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk() local
155 priv->cru, APLL); in rk3308_armclk_set_clk()
158 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
160 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
168 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
176 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
180 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
187 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
190 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
193 priv->cru, VPLL1); in rk3308_clk_get_pll_rate()
[all …]
H A Dclk_rk3368.c223 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() argument
228 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
249 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
252 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
293 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) in rk3368_mmc_get_clk() argument
312 con = readl(&cru->clksel_con[con_id]); in rk3368_mmc_get_clk()
315 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
321 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
388 struct rk3368_cru *cru = priv->cru; in rk3368_mmc_set_clk() local
409 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
[all …]
H A Dclk_rk3588.c152 struct rk3588_cru *cru = priv->cru; in rk3588_center_get_clk() local
157 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
170 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
183 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
196 con = readl(&cru->clksel_con[165]); in rk3588_center_get_clk()
218 struct rk3588_cru *cru = priv->cru; in rk3588_center_set_clk() local
231 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
244 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
257 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
270 rk_clrsetreg(&cru->clksel_con[165], in rk3588_center_set_clk()
[all …]
H A Dclk_rk3128.c93 struct rk3128_cru *cru = priv->cru; in rk3128_armclk_set_clk() local
109 priv->cru, APLL); in rk3128_armclk_set_clk()
112 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
114 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
118 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
123 rk_clrsetreg(&cru->cru_clksel_con[1], in rk3128_armclk_set_clk()
127 rk_clrsetreg(&cru->cru_clksel_con[0], in rk3128_armclk_set_clk()
132 priv->cru, APLL, hz)) in rk3128_armclk_set_clk()
136 return rockchip_pll_get_rate(&rk3128_pll_clks[APLL], priv->cru, APLL); in rk3128_armclk_set_clk()
142 struct rk3128_cru *cru = priv->cru; in rockchip_mmc_get_clk() local
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drv1106-uvc.dtsi10 &cru {
12 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
13 <&cru ARMCLK>,
14 <&cru CLK_50M_SRC>, <&cru CLK_100M_SRC>,
15 <&cru CLK_150M_SRC>, <&cru CLK_200M_SRC>,
16 <&cru CLK_250M_SRC>, <&cru CLK_300M_SRC>,
17 <&cru CLK_339M_SRC>, <&cru CLK_400M_SRC>,
18 <&cru CLK_450M_SRC>, <&cru CLK_500M_SRC>,
19 <&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
20 <&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
[all …]
H A Drv1106.dtsi5 #include <dt-bindings/clock/rv1106-cru.h>
106 clocks = <&cru ARMCLK>;
378 compatible = "rockchip,rv1106-grf-cru";
429 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
431 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
462 clocks = <&cru CLK_PVTM_CORE>;
464 resets = <&cru SRST_PVTM_CORE>, <&cru SRST_P_PVTM_CORE>;
480 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
493 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
503 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
[all …]
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
79 resets = <&cru SRST_CORE0>;
83 clocks = <&cru ARMCLK>;
91 resets = <&cru SRST_CORE1>;
95 clocks = <&cru ARMCLK>;
103 resets = <&cru SRST_CORE2>;
107 clocks = <&cru ARMCLK>;
115 resets = <&cru SRST_CORE3>;
119 clocks = <&cru ARMCLK>;
128 clocks = <&cru PLL_APLL>;
[all …]
H A Drv1106-thunder-boot.dtsi55 clocks = <&cru ACLK_ISP3P2>, <&cru HCLK_ISP3P2>,
56 <&cru CLK_CORE_ISP3P2>, <&cru ISP0CLK_VICAP>,
57 <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
58 <&cru DCLK_VICAP>, <&cru PCLK_VICAP>,
59 <&cru I0CLK_VICAP>, <&cru I1CLK_VICAP>,
60 <&cru RX0PCLK_VICAP>, <&cru RX1PCLK_VICAP>,
61 <&cru ISP0CLK_VICAP>, <&cru SCLK_VICAP_M0>,
62 <&cru SCLK_VICAP_M1>, <&cru PCLK_VICAP_VEPU>,
63 <&cru PCLK_CSIHOST0>, <&cru CLK_RXBYTECLKHS_0>,
64 <&cru PCLK_CSIHOST1>, <&cru CLK_RXBYTECLKHS_1>,
[all …]
H A Drv1126.dtsi6 #include <dt-bindings/clock/rv1126-cru.h>
57 clocks = <&cru ARMCLK>;
69 clocks = <&cru ARMCLK>;
80 clocks = <&cru ARMCLK>;
91 clocks = <&cru ARMCLK>;
125 clocks = <&cru PLL_APLL>;
766 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
768 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
787 clocks = <&cru ACLK_NPU>,
788 <&cru HCLK_NPU>,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drv1106.dtsi5 #include <dt-bindings/clock/rv1106-cru.h>
252 compatible = "rockchip,rv1106-grf-cru";
297 clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
299 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
328 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
351 clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
353 resets = <&cru SRST_M_DSM>;
369 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
380 clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
[all …]
H A Drv1126.dtsi6 #include <dt-bindings/clock/rv1126-cru.h>
53 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
73 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
573 clocks = <&cru CLK_CPUPVTM>, <&cru PCLK_CPUPVTM>;
575 resets = <&cru SRST_CPUPVTM>, <&cru SRST_CPUPVTM_P>;
594 clocks = <&cru ACLK_NPU>,
595 <&cru HCLK_NPU>,
596 <&cru PCLK_PDNPU>,
[all …]
H A Drk3568.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
65 clocks = <&cru ARMCLK>;
74 clocks = <&cru ARMCLK>;
83 clocks = <&cru ARMCLK>;
92 clocks = <&cru ARMCLK>;
212 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
213 <&cru CLK_SATA0_RXOOB>;
227 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
228 <&cru CLK_SATA1_RXOOB>;
242 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
[all …]
H A Drk3588s.dtsi6 #include <dt-bindings/clock/rk3588-cru.h>
245 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
246 <&cru ACLK_USB3OTG0>;
258 resets = <&cru SRST_A_USB3OTG0>;
278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
348 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
349 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>;
[all …]
H A Drk3528.dtsi6 #include <dt-bindings/clock/rk3528-cru.h>
359 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
360 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
361 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
362 <&cru PCLK_PCIE_PHY>;
396 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
397 <&cru SRST_PRESETN_CRU_PCIE>;
412 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
413 <&cru ACLK_USB3OTG>;
429 resets = <&cru SRST_ARESETN_USB3OTG>;
[all …]
H A Drk3588.dtsi21 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
22 <&cru ACLK_USB3OTG1>;
34 resets = <&cru SRST_A_USB3OTG1>;
74 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
76 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
100 clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>;
109 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
113 resets = <&cru SRST_M_I2S8_8CH_TX>;
126 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>;
135 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-rk628.c266 static void rk628_clk_add_lookup(struct rk628_cru *cru, struct clk *clk, in rk628_clk_add_lookup() argument
269 if (cru->clk_data.clks && id) in rk628_clk_add_lookup()
270 cru->clk_data.clks[id] = clk; in rk628_clk_add_lookup()
273 static void rk628_clk_register_muxes(struct rk628_cru *cru) in rk628_clk_register_muxes() argument
281 clk = devm_clk_regmap_register_mux(cru->dev, data->name, in rk628_clk_register_muxes()
284 cru->regmap, data->reg, in rk628_clk_register_muxes()
288 dev_err(cru->dev, "failed to register clock %s\n", in rk628_clk_register_muxes()
293 rk628_clk_add_lookup(cru, clk, data->id); in rk628_clk_register_muxes()
297 static void rk628_clk_register_gates(struct rk628_cru *cru) in rk628_clk_register_gates() argument
305 clk = devm_clk_regmap_register_gate(cru->dev, data->name, in rk628_clk_register_gates()
[all …]
H A Dclk-rk618.c164 static void rk618_clk_add_lookup(struct rk618_cru *cru, struct clk *clk, in rk618_clk_add_lookup() argument
167 if (cru->clk_data.clks && id) in rk618_clk_add_lookup()
168 cru->clk_data.clks[id] = clk; in rk618_clk_add_lookup()
171 static void rk618_clk_register_muxes(struct rk618_cru *cru) in rk618_clk_register_muxes() argument
179 clk = devm_clk_regmap_register_mux(cru->dev, data->name, in rk618_clk_register_muxes()
182 cru->regmap, data->reg, in rk618_clk_register_muxes()
186 dev_err(cru->dev, "failed to register clock %s\n", in rk618_clk_register_muxes()
191 rk618_clk_add_lookup(cru, clk, data->id); in rk618_clk_register_muxes()
195 static void rk618_clk_register_dividers(struct rk618_cru *cru) in rk618_clk_register_dividers() argument
203 clk = devm_clk_regmap_register_divider(cru->dev, data->name, in rk618_clk_register_dividers()
[all …]

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