Lines Matching refs:cru
45 clocks = <&cru ACLK_VICAP>,
46 <&cru HCLK_VICAP>,
47 <&cru DCLK_VICAP>;
51 resets = <&cru SRST_A_VICAP>,
52 <&cru SRST_H_VICAP>,
53 <&cru SRST_D_VICAP>;
57 assigned-clocks = <&cru DCLK_VICAP>;
63 rockchip,cru = <&cru>;
80 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>,
81 <&cru PCLK_MIPI_DCPHY0>,
82 <&cru PCLK_CSI_HOST_0>,
83 <&cru ICLK_CSIHOST0>;
88 resets = <&cru SRST_P_CSI_HOST_0>,
89 <&cru SRST_CSIHOST0_VICAP>;
99 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>,
100 <&cru PCLK_MIPI_DCPHY1>,
101 <&cru PCLK_CSI_HOST_1>,
102 <&cru ICLK_CSIHOST1>;
107 resets = <&cru SRST_P_CSI_HOST_1>,
108 <&cru SRST_CSIHOST1_VICAP>;
118 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>,
119 <&cru PCLK_CSIPHY0>,
120 <&cru PCLK_CSI_HOST_2>;
124 resets = <&cru SRST_CSIPHY0>,
125 <&cru SRST_P_CSIPHY0>,
126 <&cru SRST_P_CSI_HOST_2>,
127 <&cru SRST_CSIHOST2_VICAP>;
140 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>,
141 <&cru PCLK_CSIPHY1>,
142 <&cru PCLK_CSI_HOST_4>;
146 resets = <&cru SRST_CSIPHY1>,
147 <&cru SRST_P_CSIPHY1>,
148 <&cru SRST_P_CSI_HOST_4>,
149 <&cru SRST_CSIHOST4_VICAP>;
161 clocks = <&cru CLK_CIFOUT_OUT>;