Lines Matching refs:cru
16 assigned-clocks = <&cru SCLK_EMMC>;
17 assigned-clock-parents = <&cru PLL_GPLL>;
22 assigned-clocks = <&cru SCLK_UART0_SRC>;
23 assigned-clock-parents = <&cru PLL_GPLL>;
27 assigned-clocks = <&cru SCLK_UART_SRC>;
28 assigned-clock-parents = <&cru PLL_GPLL>;
32 assigned-clocks = <&cru SCLK_UART_SRC>;
33 assigned-clock-parents = <&cru PLL_GPLL>;
37 assigned-clocks = <&cru SCLK_UART_SRC>;
38 assigned-clock-parents = <&cru PLL_GPLL>;
47 assigned-clocks = <&cru SCLK_SPDIF_DIV>;
48 assigned-clock-parents = <&cru PLL_GPLL>;
52 assigned-clocks = <&cru SCLK_I2S0_DIV>;
53 assigned-clock-parents = <&cru PLL_GPLL>;
57 assigned-clocks = <&cru SCLK_I2S1_DIV>;
58 assigned-clock-parents = <&cru PLL_GPLL>;
62 assigned-clocks = <&cru SCLK_I2S2_DIV>;
63 assigned-clock-parents = <&cru PLL_GPLL>;
66 &cru {
68 <&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
69 <&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>,
70 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
71 <&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
72 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
73 <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
74 <&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
75 <&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
76 <&cru ARMCLKL>, <&cru ARMCLKB>,
77 <&cru PLL_NPLL>, <&cru ACLK_GPU>,
78 <&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
79 <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
80 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
81 <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
82 <&cru PCLK_PERILP1>, <&cru SCLK_I2C1>,
83 <&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
84 <&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
85 <&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
86 <&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
87 <&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
88 <&cru ACLK_GIC>, <&cru ACLK_ISP0>,
89 <&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
90 <&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
91 <&cru ACLK_HDCP>, <&cru ACLK_VIO>,
92 <&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
93 <&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
94 <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
95 <&cru ACLK_IEP>, <&cru ACLK_RGA>,
96 <&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
97 <&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
98 <&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
99 <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
100 <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
101 <&cru PCLK_ALIVE>, <&cru SCLK_CS>,
102 <&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>,
103 <&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
104 <&cru HCLK_VOP1>;