1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 compatible = "rockchip,rk3588"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet1 = &gmac1; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 i2c6 = &i2c6; 29 i2c7 = &i2c7; 30 i2c8 = &i2c8; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 serial6 = &uart6; 38 serial7 = &uart7; 39 serial8 = &uart8; 40 serial9 = &uart9; 41 spi0 = &spi0; 42 spi1 = &spi1; 43 spi2 = &spi2; 44 spi3 = &spi3; 45 spi4 = &spi4; 46 spi5 = &sfc; 47 gpio0 = &gpio0; 48 gpio1 = &gpio1; 49 gpio2 = &gpio2; 50 gpio3 = &gpio3; 51 gpio4 = &gpio4; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu_l0>; 62 }; 63 core1 { 64 cpu = <&cpu_l1>; 65 }; 66 core2 { 67 cpu = <&cpu_l2>; 68 }; 69 core3 { 70 cpu = <&cpu_l3>; 71 }; 72 }; 73 cluster1 { 74 core0 { 75 cpu = <&cpu_b0>; 76 }; 77 core1 { 78 cpu = <&cpu_b1>; 79 }; 80 }; 81 cluster2 { 82 core0 { 83 cpu = <&cpu_b2>; 84 }; 85 core1 { 86 cpu = <&cpu_b3>; 87 }; 88 }; 89 }; 90 91 cpu_l0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 capacity-dmips-mhz = <530>; 97 }; 98 99 cpu_l1: cpu@100 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x100>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <530>; 105 }; 106 107 cpu_l2: cpu@200 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x200>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <530>; 113 }; 114 115 cpu_l3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x300>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <530>; 121 }; 122 123 cpu_b0: cpu@400 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x400>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <1024>; 129 }; 130 131 cpu_b1: cpu@500 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a76"; 134 reg = <0x500>; 135 enable-method = "psci"; 136 capacity-dmips-mhz = <1024>; 137 }; 138 139 cpu_b2: cpu@600 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a76"; 142 reg = <0x600>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 }; 146 147 cpu_b3: cpu@700 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a76"; 150 reg = <0x700>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <1024>; 153 }; 154 }; 155 156 arm_pmu: arm-pmu { 157 compatible = "arm,armv8-pmuv3"; 158 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>; 159 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 160 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 161 }; 162 163 firmware: firmware { 164 optee: optee { 165 compatible = "linaro,optee-tz"; 166 method = "smc"; 167 }; 168 169 scmi: scmi { 170 compatible = "arm,scmi-smc"; 171 shmem = <&scmi_shmem>; 172 arm,smc-id = <0x82000010>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 scmi_clk: protocol@14 { 177 reg = <0x14>; 178 #clock-cells = <1>; 179 180 assigned-clocks = <&scmi_clk SCMI_SPLL>; 181 assigned-clock-rates = <700000000>; 182 }; 183 184 scmi_reset: protocol@16 { 185 reg = <0x16>; 186 #reset-cells = <1>; 187 }; 188 }; 189 190 sdei: sdei { 191 compatible = "arm,sdei-1.0"; 192 method = "smc"; 193 }; 194 }; 195 196 psci: psci { 197 compatible = "arm,psci-1.0"; 198 method = "smc"; 199 }; 200 201 spll: spll { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <702000000>; 205 clock-output-names = "spll"; 206 }; 207 208 timer { 209 compatible = "arm,armv8-timer"; 210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 214 }; 215 216 xin32k: xin32k { 217 compatible = "fixed-clock"; 218 #clock-cells = <0>; 219 clock-frequency = <32768>; 220 clock-output-names = "xin32k"; 221 }; 222 223 xin24m: xin24m { 224 compatible = "fixed-clock"; 225 #clock-cells = <0>; 226 clock-frequency = <24000000>; 227 clock-output-names = "xin24m"; 228 }; 229 230 sram: sram@10f000 { 231 compatible = "mmio-sram"; 232 reg = <0x0 0x0010f000 0x0 0x100>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges = <0 0x0 0x0010f000 0x100>; 236 237 scmi_shmem: scmi_shmem@0 { 238 compatible = "arm,scmi-shmem"; 239 reg = <0x0 0x100>; 240 }; 241 }; 242 243 usbdrd3_0: usbdrd3_0 { 244 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 245 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 246 <&cru ACLK_USB3OTG0>; 247 clock-names = "ref", "suspend", "bus"; 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges; 251 status = "disabled"; 252 253 usbdrd_dwc3_0: usb@fc000000 { 254 compatible = "snps,dwc3"; 255 reg = <0x0 0xfc000000 0x0 0x400000>; 256 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 257 power-domains = <&power RK3588_PD_USB>; 258 resets = <&cru SRST_A_USB3OTG0>; 259 reset-names = "usb3-otg"; 260 dr_mode = "otg"; 261 phys = <&u2phy0_otg>; 262 phy-names = "usb2-phy"; 263 phy_type = "utmi_wide"; 264 snps,dis_enblslpm_quirk; 265 snps,dis-u1-entry-quirk; 266 snps,dis-u2-entry-quirk; 267 snps,dis-u2-freeclk-exists-quirk; 268 snps,dis-del-phy-power-chg-quirk; 269 snps,dis-tx-ipgap-linecheck-quirk; 270 status = "disabled"; 271 }; 272 }; 273 274 usb_host0_ehci: usb@fc800000 { 275 compatible = "generic-ehci"; 276 reg = <0x0 0xfc800000 0x0 0x40000>; 277 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 279 clock-names = "usbhost", "arbiter"; 280 phys = <&u2phy2_host>; 281 phy-names = "usb2-phy"; 282 power-domains = <&power RK3588_PD_USB>; 283 status = "disabled"; 284 }; 285 286 usb_host0_ohci: usb@fc840000 { 287 compatible = "generic-ohci"; 288 reg = <0x0 0xfc840000 0x0 0x40000>; 289 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; 291 clock-names = "usbhost", "arbiter"; 292 phys = <&u2phy2_host>; 293 phy-names = "usb2-phy"; 294 power-domains = <&power RK3588_PD_USB>; 295 status = "disabled"; 296 }; 297 298 usb_host1_ehci: usb@fc880000 { 299 compatible = "generic-ehci"; 300 reg = <0x0 0xfc880000 0x0 0x40000>; 301 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 303 clock-names = "usbhost", "arbiter"; 304 phys = <&u2phy3_host>; 305 phy-names = "usb2-phy"; 306 power-domains = <&power RK3588_PD_USB>; 307 status = "disabled"; 308 }; 309 310 usb_host1_ohci: usb@fc8c0000 { 311 compatible = "generic-ohci"; 312 reg = <0x0 0xfc8c0000 0x0 0x40000>; 313 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; 315 clock-names = "usbhost", "arbiter"; 316 phys = <&u2phy3_host>; 317 phy-names = "usb2-phy"; 318 power-domains = <&power RK3588_PD_USB>; 319 status = "disabled"; 320 }; 321 322 mmu600_pcie: iommu@fc900000 { 323 compatible = "arm,smmu-v3"; 324 reg = <0x0 0xfc900000 0x0 0x200000>; 325 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 329 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 330 #iommu-cells = <1>; 331 status = "disabled"; 332 }; 333 334 mmu600_php: iommu@fcb00000 { 335 compatible = "arm,smmu-v3"; 336 reg = <0x0 0xfcb00000 0x0 0x200000>; 337 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 341 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 342 #iommu-cells = <1>; 343 status = "disabled"; 344 }; 345 346 usbhost3_0: usbhost3_0 { 347 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 348 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 349 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>; 350 clock-names = "ref", "suspend", "bus", "utmi"; 351 #address-cells = <2>; 352 #size-cells = <2>; 353 ranges; 354 status = "disabled"; 355 356 usbhost_dwc3_0: usb@fcd00000 { 357 compatible = "snps,dwc3"; 358 reg = <0x0 0xfcd00000 0x0 0x400000>; 359 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 360 power-domains = <&power RK3588_PD_PHP>; 361 resets = <&cru SRST_A_USB3OTG2>; 362 reset-names = "usb3-host"; 363 dr_mode = "host"; 364 phy_type = "utmi_wide"; 365 snps,dis_enblslpm_quirk; 366 snps,dis-u2-freeclk-exists-quirk; 367 snps,dis-del-phy-power-chg-quirk; 368 snps,dis-tx-ipgap-linecheck-quirk; 369 status = "disabled"; 370 }; 371 }; 372 373 sys_grf: syscon@fd58c000 { 374 compatible = "rockchip,rk3588-sys-grf", "syscon"; 375 reg = <0x0 0xfd58c000 0x0 0x1000>; 376 }; 377 378 vo0_grf: syscon@fd5a6000 { 379 compatible = "rockchip,rk3588-vo-grf", "syscon"; 380 reg = <0x0 0xfd5a6000 0x0 0x2000>; 381 }; 382 383 vo1_grf: syscon@fd5a8000 { 384 compatible = "rockchip,rk3588-vo-grf", "syscon"; 385 reg = <0x0 0xfd5a8000 0x0 0x100>; 386 }; 387 388 usb_grf: syscon@fd5ac000 { 389 compatible = "rockchip,rk3588-usb-grf", "syscon"; 390 reg = <0x0 0xfd5ac000 0x0 0x4000>; 391 }; 392 393 php_grf: syscon@fd5b0000 { 394 compatible = "rockchip,rk3588-php-grf", "syscon"; 395 reg = <0x0 0xfd5b0000 0x0 0x1000>; 396 }; 397 398 pipe_phy0_grf: syscon@fd5bc000 { 399 compatible = "rockchip,pipe-phy-grf", "syscon"; 400 reg = <0x0 0xfd5bc000 0x0 0x100>; 401 }; 402 403 pipe_phy2_grf: syscon@fd5c4000 { 404 compatible = "rockchip,pipe-phy-grf", "syscon"; 405 reg = <0x0 0xfd5c4000 0x0 0x100>; 406 }; 407 408 usbdpphy0_grf: syscon@fd5c8000 { 409 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 410 reg = <0x0 0xfd5c8000 0x0 0x4000>; 411 }; 412 413 usb2phy0_grf: syscon@fd5d0000 { 414 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 415 "simple-mfd"; 416 reg = <0x0 0xfd5d0000 0x0 0x4000>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 420 u2phy0: usb2-phy@0 { 421 compatible = "rockchip,rk3588-usb2phy"; 422 reg = <0x0 0x10>; 423 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 424 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 425 reset-names = "phy", "apb"; 426 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 427 clock-names = "phyclk"; 428 #clock-cells = <0>; 429 status = "disabled"; 430 431 u2phy0_otg: otg-port { 432 #phy-cells = <0>; 433 status = "disabled"; 434 }; 435 }; 436 }; 437 438 usb2phy2_grf: syscon@fd5d8000 { 439 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 440 "simple-mfd"; 441 reg = <0x0 0xfd5d8000 0x0 0x4000>; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 445 u2phy2: usb2-phy@8000 { 446 compatible = "rockchip,rk3588-usb2phy"; 447 reg = <0x8000 0x10>; 448 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 449 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 450 reset-names = "phy", "apb"; 451 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 452 clock-names = "phyclk"; 453 #clock-cells = <0>; 454 status = "disabled"; 455 456 u2phy2_host: host-port { 457 #phy-cells = <0>; 458 status = "disabled"; 459 }; 460 }; 461 }; 462 463 usb2phy3_grf: syscon@fd5dc000 { 464 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 465 "simple-mfd"; 466 reg = <0x0 0xfd5dc000 0x0 0x4000>; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 470 u2phy3: usb2-phy@c000 { 471 compatible = "rockchip,rk3588-usb2phy"; 472 reg = <0xc000 0x10>; 473 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 474 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 475 reset-names = "phy", "apb"; 476 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 477 clock-names = "phyclk"; 478 #clock-cells = <0>; 479 status = "disabled"; 480 481 u2phy3_host: host-port { 482 #phy-cells = <0>; 483 status = "disabled"; 484 }; 485 }; 486 }; 487 488 hdptxphy0_grf: syscon@fd5e0000 { 489 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 490 reg = <0x0 0xfd5e0000 0x0 0x100>; 491 }; 492 493 ioc: syscon@fd5f0000 { 494 compatible = "rockchip,rk3588-ioc", "syscon"; 495 reg = <0x0 0xfd5f0000 0x0 0x10000>; 496 }; 497 498 syssram: sram@fd600000 { 499 compatible = "mmio-sram"; 500 reg = <0x0 0xfd600000 0x0 0x100000>; 501 502 #address-cells = <1>; 503 #size-cells = <1>; 504 ranges = <0x0 0x0 0xfd600000 0x100000>; 505 }; 506 507 cru: clock-controller@fd7c0000 { 508 compatible = "rockchip,rk3588-cru"; 509 rockchip,grf = <&php_grf>; 510 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 511 #clock-cells = <1>; 512 #reset-cells = <1>; 513 514 assigned-clocks = 515 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 516 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 517 <&cru ARMCLK_L>, <&cru ARMCLK_B01>, 518 <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, 519 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 520 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 521 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 522 <&cru HCLK_PMU_CM0_ROOT>; 523 assigned-clock-rates = 524 <100000000>, <1500000000>, 525 <850000000>, <1188000000>, 526 <816000000>, <1008000000>, 527 <600000000>, <200000000>, 528 <400000000>, <500000000>, 529 <800000000>, <100000000>, 530 <400000000>, <100000000>, 531 <200000000>; 532 }; 533 534 i2c0: i2c@fd880000 { 535 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 536 reg = <0x0 0xfd880000 0x0 0x1000>; 537 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 538 clock-names = "i2c", "pclk"; 539 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2c0m0_xfer>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 status = "disabled"; 545 }; 546 547 uart0: serial@fd890000 { 548 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 549 reg = <0x0 0xfd890000 0x0 0x100>; 550 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 552 clock-names = "baudclk", "apb_pclk"; 553 reg-shift = <2>; 554 reg-io-width = <4>; 555 dmas = <&dmac0 6>, <&dmac0 7>; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&uart0m0_xfer>; 558 status = "disabled"; 559 }; 560 561 pwm0: pwm@fd8b0000 { 562 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 563 reg = <0x0 0xfd8b0000 0x0 0x10>; 564 #pwm-cells = <3>; 565 pinctrl-names = "active"; 566 pinctrl-0 = <&pwm0m0_pins>; 567 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 568 clock-names = "pwm", "pclk"; 569 status = "disabled"; 570 }; 571 572 pwm1: pwm@fd8b0010 { 573 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 574 reg = <0x0 0xfd8b0010 0x0 0x10>; 575 #pwm-cells = <3>; 576 pinctrl-names = "active"; 577 pinctrl-0 = <&pwm1m0_pins>; 578 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 579 clock-names = "pwm", "pclk"; 580 status = "disabled"; 581 }; 582 583 pwm2: pwm@fd8b0020 { 584 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 585 reg = <0x0 0xfd8b0020 0x0 0x10>; 586 #pwm-cells = <3>; 587 pinctrl-names = "active"; 588 pinctrl-0 = <&pwm2m0_pins>; 589 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 590 clock-names = "pwm", "pclk"; 591 status = "disabled"; 592 }; 593 594 pwm3: pwm@fd8b0030 { 595 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 596 reg = <0x0 0xfd8b0030 0x0 0x10>; 597 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 599 #pwm-cells = <3>; 600 pinctrl-names = "active"; 601 pinctrl-0 = <&pwm3m0_pins>; 602 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 603 clock-names = "pwm", "pclk"; 604 status = "disabled"; 605 }; 606 607 pmu: power-management@fd8d8000 { 608 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 609 reg = <0x0 0xfd8d8000 0x0 0x400>; 610 611 power: power-controller { 612 compatible = "rockchip,rk3588-power-controller"; 613 #power-domain-cells = <1>; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 status = "okay"; 617 618 /* These power domains are grouped by VD_NPU */ 619 power-domain@RK3588_PD_NPU { 620 reg = <RK3588_PD_NPU>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 624 power-domain@RK3588_PD_NPUTOP { 625 reg = <RK3588_PD_NPUTOP>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 629 power-domain@RK3588_PD_NPU1 { 630 reg = <RK3588_PD_NPU1>; 631 }; 632 power-domain@RK3588_PD_NPU2 { 633 reg = <RK3588_PD_NPU2>; 634 }; 635 }; 636 }; 637 /* These power domains are grouped by VD_GPU */ 638 power-domain@RK3588_PD_GPU { 639 reg = <RK3588_PD_GPU>; 640 }; 641 /* These power domains are grouped by VD_VCODEC */ 642 power-domain@RK3588_PD_VCODEC { 643 reg = <RK3588_PD_VCODEC>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 647 power-domain@RK3588_PD_RKVDEC0 { 648 reg = <RK3588_PD_RKVDEC0>; 649 }; 650 power-domain@RK3588_PD_RKVDEC1 { 651 reg = <RK3588_PD_RKVDEC1>; 652 }; 653 power-domain@RK3588_PD_VENC0 { 654 reg = <RK3588_PD_VENC0>; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 658 power-domain@RK3588_PD_VENC1 { 659 reg = <RK3588_PD_VENC1>; 660 }; 661 }; 662 }; 663 /* These power domains are grouped by VD_LOGIC */ 664 power-domain@RK3588_PD_VDPU { 665 reg = <RK3588_PD_VDPU>; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 669 power-domain@RK3588_PD_RGA30 { 670 reg = <RK3588_PD_RGA30>; 671 }; 672 power-domain@RK3588_PD_av1 { 673 reg = <RK3588_PD_AV1>; 674 }; 675 }; 676 power-domain@RK3588_PD_VOP { 677 reg = <RK3588_PD_VOP>; 678 }; 679 power-domain@RK3588_PD_VO0 { 680 reg = <RK3588_PD_VO0>; 681 }; 682 power-domain@RK3588_PD_VO1 { 683 reg = <RK3588_PD_VO1>; 684 }; 685 power-domain@RK3588_PD_VI { 686 reg = <RK3588_PD_VI>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 690 power-domain@RK3588_PD_ISP1 { 691 reg = <RK3588_PD_ISP1>; 692 }; 693 power-domain@RK3588_PD_FEC { 694 reg = <RK3588_PD_FEC>; 695 }; 696 }; 697 power-domain@RK3588_PD_RGA31 { 698 reg = <RK3588_PD_RGA31>; 699 }; 700 power-domain@RK3588_PD_USB { 701 reg = <RK3588_PD_USB>; 702 }; 703 power-domain@RK3588_PD_PHP { 704 reg = <RK3588_PD_PHP>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 power-domain@RK3588_PD_GMAC { 709 reg = <RK3588_PD_GMAC>; 710 }; 711 power-domain@RK3588_PD_PCIE { 712 reg = <RK3588_PD_PCIE>; 713 }; 714 }; 715 power-domain@RK3588_PD_NVM { 716 reg = <RK3588_PD_NVM>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 power-domain@RK3588_PD_NVM0 { 721 reg = <RK3588_PD_NVM0>; 722 }; 723 }; 724 power-domain@RK3588_PD_SDIO { 725 reg = <RK3588_PD_SDIO>; 726 }; 727 power-domain@RK3588_PD_AUDIO { 728 reg = <RK3588_PD_AUDIO>; 729 }; 730 power-domain@RK3588_PD_SDMMC { 731 reg = <RK3588_PD_SDMMC>; 732 }; 733 }; 734 }; 735 736 pvtm@fda40000 { 737 compatible = "rockchip,rk3588-bigcore0-pvtm"; 738 reg = <0x0 0xfda40000 0x0 0x100>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 pvtm@0 { 742 reg = <0>; 743 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 744 clock-names = "clk", "pclk"; 745 }; 746 }; 747 748 pvtm@fda50000 { 749 compatible = "rockchip,rk3588-bigcore1-pvtm"; 750 reg = <0x0 0xfda50000 0x0 0x100>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 pvtm@1 { 754 reg = <1>; 755 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 756 clock-names = "clk", "pclk"; 757 }; 758 }; 759 760 pvtm@fda60000 { 761 compatible = "rockchip,rk3588-litcore-pvtm"; 762 reg = <0x0 0xfda60000 0x0 0x100>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 pvtm@2 { 766 reg = <2>; 767 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 768 clock-names = "clk", "pclk"; 769 }; 770 }; 771 772 pvtm@fdaf0000 { 773 compatible = "rockchip,rk3588-npu-pvtm"; 774 reg = <0x0 0xfdaf0000 0x0 0x100>; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 pvtm@3 { 778 reg = <3>; 779 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 780 clock-names = "clk", "pclk"; 781 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 782 reset-names = "rts", "rst-p"; 783 }; 784 }; 785 786 pvtm@fdb30000 { 787 compatible = "rockchip,rk3588-gpu-pvtm"; 788 reg = <0x0 0xfdb30000 0x0 0x100>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 pvtm@4 { 792 reg = <4>; 793 clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; 794 clock-names = "clk", "pclk"; 795 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 796 reset-names = "rts", "rst-p"; 797 }; 798 }; 799 800 npu0_mmu: iommu@fdab9000 { 801 compatible = "rockchip,iommu-v2"; 802 reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>; 803 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 804 interrupt-names = "npu0_mmu"; 805 clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; 806 clock-names = "aclk", "iface"; 807 power-domains = <&power RK3588_PD_NPUTOP>; 808 #iommu-cells = <0>; 809 status = "disabled"; 810 }; 811 812 npu1_mmu: iommu@fdaca000 { 813 compatible = "rockchip,iommu-v2"; 814 reg = <0x0 0xfdaca000 0x0 0x100>; 815 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "npu1_mmu"; 817 clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; 818 clock-names = "aclk", "iface"; 819 power-domains = <&power RK3588_PD_NPU1>; 820 #iommu-cells = <0>; 821 status = "disabled"; 822 }; 823 824 npu2_mmu: iommu@fdada000 { 825 compatible = "rockchip,iommu-v2"; 826 reg = <0x0 0xfdada000 0x0 0x100>; 827 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 828 interrupt-names = "npu2_mmu"; 829 clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; 830 clock-names = "aclk", "iface"; 831 power-domains = <&power RK3588_PD_NPU2>; 832 #iommu-cells = <0>; 833 status = "disabled"; 834 }; 835 836 vdpu_mmu: iommu@fdb50800 { 837 compatible = "rockchip,iommu-v2"; 838 reg = <0x0 0xfdb50800 0x0 0x40>; 839 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "irq_vdpu_mmu"; 841 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 842 clock-names = "aclk", "iface"; 843 power-domains = <&power RK3588_PD_VDPU>; 844 #iommu-cells = <0>; 845 status = "disabled"; 846 }; 847 848 rga3_0_mmu: iommu@fdb60f00 { 849 compatible = "rockchip,iommu-v2"; 850 reg = <0x0 0xfdb60f00 0x0 0x100>; 851 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-names = "rga3_0_mmu"; 853 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 854 clock-names = "aclk", "iface"; 855 power-domains = <&power RK3588_PD_RGA30>; 856 #iommu-cells = <0>; 857 status = "disabled"; 858 }; 859 860 rga3_1_mmu: iommu@fdb70f00 { 861 compatible = "rockchip,iommu-v2"; 862 reg = <0x0 0xfdb70f00 0x0 0x100>; 863 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "rga3_1_mmu"; 865 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 866 clock-names = "aclk", "iface"; 867 power-domains = <&power RK3588_PD_RGA31>; 868 #iommu-cells = <0>; 869 status = "disabled"; 870 }; 871 872 jpegd_mmu: iommu@fdb90480 { 873 compatible = "rockchip,iommu-v2"; 874 reg = <0x0 0xfdb90480 0x0 0x40>; 875 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 876 interrupt-names = "irq_jpegd_mmu"; 877 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 878 clock-names = "aclk", "iface"; 879 power-domains = <&power RK3588_PD_VDPU>; 880 #iommu-cells = <0>; 881 status = "disabled"; 882 }; 883 884 jpege0_mmu: iommu@fdba0800 { 885 compatible = "rockchip,iommu-v2"; 886 reg = <0x0 0xfdba0800 0x0 0x40>; 887 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "irq_jpege0_mmu"; 889 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 890 clock-names = "aclk", "iface"; 891 power-domains = <&power RK3588_PD_VDPU>; 892 #iommu-cells = <0>; 893 status = "disabled"; 894 }; 895 896 jpege1_mmu: iommu@fdba4800 { 897 compatible = "rockchip,iommu-v2"; 898 reg = <0x0 0xfdba4800 0x0 0x40>; 899 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "irq_jpege1_mmu"; 901 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 902 clock-names = "aclk", "iface"; 903 power-domains = <&power RK3588_PD_VDPU>; 904 #iommu-cells = <0>; 905 status = "disabled"; 906 }; 907 908 jpege2_mmu: iommu@fdba8800 { 909 compatible = "rockchip,iommu-v2"; 910 reg = <0x0 0xfdba8800 0x0 0x40>; 911 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 912 interrupt-names = "irq_jpege2_mmu"; 913 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 914 clock-names = "aclk", "iface"; 915 power-domains = <&power RK3588_PD_VDPU>; 916 #iommu-cells = <0>; 917 status = "disabled"; 918 }; 919 920 jpege3_mmu: iommu@fdbac800 { 921 compatible = "rockchip,iommu-v2"; 922 reg = <0x0 0xfdbac800 0x0 0x40>; 923 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 924 interrupt-names = "irq_jpege3_mmu"; 925 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 926 clock-names = "aclk", "iface"; 927 power-domains = <&power RK3588_PD_VDPU>; 928 #iommu-cells = <0>; 929 status = "disabled"; 930 }; 931 932 iep_mmu: iommu@fdbb0800 { 933 compatible = "rockchip,iommu-v2"; 934 reg = <0x0 0xfdbb0800 0x0 0x100>; 935 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-names = "irq_iep_mmu"; 937 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 938 clock-names = "aclk", "iface"; 939 #iommu-cells = <0>; 940 power-domains = <&power RK3588_PD_VDPU>; 941 status = "disabled"; 942 }; 943 944 rkvenc0_mmu: iommu@fdbdf000 { 945 compatible = "rockchip,iommu-v2"; 946 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 947 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 950 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 951 clock-names = "aclk", "iface"; 952 rockchip,disable-mmu-reset; 953 rockchip,enable-cmd-retry; 954 #iommu-cells = <0>; 955 power-domains = <&power RK3588_PD_VENC0>; 956 status = "disabled"; 957 }; 958 959 rkvenc1_mmu: iommu@fdbef000 { 960 compatible = "rockchip,iommu-v2"; 961 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 962 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 964 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 965 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 966 lock-names = "aclk", "iface"; 967 rockchip,disable-mmu-reset; 968 rockchip,enable-cmd-retry; 969 #iommu-cells = <0>; 970 power-domains = <&power RK3588_PD_VENC1>; 971 status = "disabled"; 972 }; 973 974 rkvdec0_mmu: iommu@fdc38700 { 975 compatible = "rockchip,iommu-v2"; 976 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 977 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "irq_rkvdec0_mmu"; 979 locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 980 clock-names = "aclk", "iface"; 981 rockchip,disable-mmu-reset; 982 rockchip,enable-cmd-retry; 983 #iommu-cells = <0>; 984 power-domains = <&power RK3588_PD_RKVDEC0>; 985 status = "disabled"; 986 }; 987 988 rkvdec1_mmu: iommu@fdc48700 { 989 compatible = "rockchip,iommu-v2"; 990 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 991 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-names = "irq_rkvdec1_mmu"; 993 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 994 clock-names = "aclk", "iface"; 995 rockchip,disable-mmu-reset; 996 rockchip,enable-cmd-retry; 997 #iommu-cells = <0>; 998 power-domains = <&power RK3588_PD_RKVDEC1>; 999 status = "disabled"; 1000 }; 1001 1002 isp0_mmu: iommu@fdcb7f00 { 1003 compatible = "rockchip,iommu-v2"; 1004 reg = <0x0 0xfdcb7f00 0x0 0x100>; 1005 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupt-names = "isp0_mmu"; 1007 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 1008 clock-names = "aclk", "iface"; 1009 power-domains = <&power RK3588_PD_VI>; 1010 #iommu-cells = <0>; 1011 rockchip,disable-mmu-reset; 1012 status = "disabled"; 1013 }; 1014 1015 isp1_mmu: iommu@fdcc7f00 { 1016 compatible = "rockchip,iommu-v2"; 1017 reg = <0x0 0xfdcc7f00 0x0 0x100>; 1018 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "isp1_mmu"; 1020 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 1021 clock-names = "aclk", "iface"; 1022 power-domains = <&power RK3588_PD_ISP1>; 1023 #iommu-cells = <0>; 1024 rockchip,disable-mmu-reset; 1025 status = "disabled"; 1026 }; 1027 1028 fec0_mmu: iommu@fdcd0f00 { 1029 compatible = "rockchip,iommu-v2"; 1030 reg = <0x0 0xfdcd0f00 0x0 0x100>; 1031 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1032 interrupt-names = "fec0_mmu"; 1033 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>; 1034 clock-names = "aclk", "iface"; 1035 power-domains = <&power RK3588_PD_FEC>; 1036 #iommu-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 fec1_mmu: iommu@fdcd8f00 { 1041 compatible = "rockchip,iommu-v2"; 1042 reg = <0x0 0xfdcd8f00 0x0 0x100>; 1043 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "fec1_mmu"; 1045 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>; 1046 clock-names = "aclk", "iface"; 1047 power-domains = <&power RK3588_PD_FEC>; 1048 #iommu-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 vop_mmu: iommu@fdd97e00 { 1053 compatible = "rockchip,iommu-v2"; 1054 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 1055 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1056 interrupt-names = "vop_mmu"; 1057 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1058 clock-names = "aclk", "iface"; 1059 #iommu-cells = <0>; 1060 rockchip,disable-device-link-resume; 1061 status = "disabled"; 1062 }; 1063 1064 spdif_tx2: spdif-tx@fddb0000 { 1065 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1066 reg = <0x0 0xfddb0000 0x0 0x1000>; 1067 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&dmac1 6>; 1069 dma-names = "tx"; 1070 clock-names = "mclk", "hclk"; 1071 clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; 1072 #sound-dai-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 i2s4_8ch: i2s@fddc0000 { 1077 compatible = "rockchip,rk3588-i2s-tdm"; 1078 reg = <0x0 0xfddc0000 0x0 0x1000>; 1079 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 1081 clock-names = "mclk_tx", "hclk"; 1082 dmas = <&dmac2 0>; 1083 dma-names = "tx"; 1084 resets = <&cru SRST_M_I2S4_8CH_TX>; 1085 reset-names = "tx-m"; 1086 #sound-dai-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 spdif_tx3: spdif-tx@fdde0000 { 1091 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1092 reg = <0x0 0xfdde0000 0x0 0x1000>; 1093 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1094 dmas = <&dmac1 7>; 1095 dma-names = "tx"; 1096 clock-names = "mclk", "hclk"; 1097 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 1098 #sound-dai-cells = <0>; 1099 status = "disabled"; 1100 }; 1101 1102 i2s5_8ch: i2s@fddf0000 { 1103 compatible = "rockchip,rk3588-i2s-tdm"; 1104 reg = <0x0 0xfddf0000 0x0 0x1000>; 1105 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1106 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 1107 clock-names = "mclk_tx", "hclk"; 1108 dmas = <&dmac2 2>; 1109 dma-names = "tx"; 1110 resets = <&cru SRST_M_I2S5_8CH_TX>; 1111 reset-names = "tx-m"; 1112 #sound-dai-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2s9_8ch: i2s@fddfc000 { 1117 compatible = "rockchip,rk3588-i2s-tdm"; 1118 reg = <0x0 0xfddfc000 0x0 0x1000>; 1119 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 1121 clock-names = "mclk_rx", "hclk"; 1122 dmas = <&dmac2 23>; 1123 dma-names = "rx"; 1124 resets = <&cru SRST_M_I2S9_8CH_RX>; 1125 reset-names = "rx-m"; 1126 #sound-dai-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 spdif_rx0: spdif-rx@fde08000 { 1131 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 1132 reg = <0x0 0xfde08000 0x0 0x1000>; 1133 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 1135 clock-names = "mclk", "hclk"; 1136 dmas = <&dmac0 21>; 1137 dma-names = "rx"; 1138 resets = <&cru SRST_M_SPDIFRX0>; 1139 reset-names = "spdifrx-m"; 1140 #sound-dai-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 edp0: edp@fdec0000 { 1145 compatible = "rockchip,rk3588-edp"; 1146 reg = <0x0 0xfdec0000 0x0 0x1000>; 1147 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 1149 <&cru CLK_EDP0_200M>; 1150 clock-names = "dp", "pclk", "spdif"; 1151 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 1152 reset-names = "dp", "apb"; 1153 phys = <&hdptxphy0>; 1154 phy-names = "dp"; 1155 power-domains = <&power RK3588_PD_VO1>; 1156 rockchip,grf = <&vo1_grf>; 1157 status = "disabled"; 1158 }; 1159 1160 pcie2x1l1: pcie@fe180000 { 1161 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1162 #address-cells = <3>; 1163 #size-cells = <2>; 1164 bus-range = <0x30 0x3f>; 1165 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 1166 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 1167 <&cru CLK_PCIE_AUX3>; 1168 clock-names = "aclk_mst", "aclk_slv", 1169 "aclk_dbi", "pclk", "aux"; 1170 device_type = "pci"; 1171 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1177 #interrupt-cells = <1>; 1178 interrupt-map-mask = <0 0 0 7>; 1179 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 1180 <0 0 0 2 &pcie2x1l1_intc 1>, 1181 <0 0 0 3 &pcie2x1l1_intc 2>, 1182 <0 0 0 4 &pcie2x1l1_intc 3>; 1183 linux,pci-domain = <3>; 1184 num-ib-windows = <8>; 1185 num-ob-windows = <8>; 1186 max-link-speed = <2>; 1187 msi-map = <0x3000 &its 0x3000 0x1000>; 1188 num-lanes = <1>; 1189 phys = <&combphy2_psu PHY_TYPE_PCIE>; 1190 phy-names = "pcie-phy"; 1191 power-domains = <&power RK3588_PD_PHP>; 1192 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 1193 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 1194 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 1195 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 1196 1197 reg = <0xa 0x40c00000 0x0 0x400000>, 1198 <0x0 0xfe180000 0x0 0x10000>; 1199 reg-names = "pcie-dbi", "pcie-apb"; 1200 resets = <&cru SRST_PCIE3_POWER_UP>; 1201 reset-names = "pipe"; 1202 status = "disabled"; 1203 1204 pcie2x1l1_intc: legacy-interrupt-controller { 1205 interrupt-controller; 1206 #address-cells = <0>; 1207 #interrupt-cells = <1>; 1208 interrupt-parent = <&gic>; 1209 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 1210 }; 1211 }; 1212 1213 pcie2x1l2: pcie@fe190000 { 1214 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 1215 #address-cells = <3>; 1216 #size-cells = <2>; 1217 bus-range = <0x40 0x4f>; 1218 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 1219 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 1220 <&cru CLK_PCIE_AUX4>; 1221 clock-names = "aclk_mst", "aclk_slv", 1222 "aclk_dbi", "pclk", "aux"; 1223 device_type = "pci"; 1224 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1229 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 1230 #interrupt-cells = <1>; 1231 interrupt-map-mask = <0 0 0 7>; 1232 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 1233 <0 0 0 2 &pcie2x1l2_intc 1>, 1234 <0 0 0 3 &pcie2x1l2_intc 2>, 1235 <0 0 0 4 &pcie2x1l2_intc 3>; 1236 linux,pci-domain = <4>; 1237 num-ib-windows = <8>; 1238 num-ob-windows = <8>; 1239 max-link-speed = <2>; 1240 msi-map = <0x4000 &its 0x4000 0x1000>; 1241 num-lanes = <1>; 1242 phys = <&combphy0_ps PHY_TYPE_PCIE>; 1243 phy-names = "pcie-phy"; 1244 power-domains = <&power RK3588_PD_PHP>; 1245 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 1246 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 1247 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 1248 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 1249 reg = <0xa 0x41000000 0x0 0x400000>, 1250 <0x0 0xfe190000 0x0 0x10000>; 1251 reg-names = "pcie-dbi", "pcie-apb"; 1252 resets = <&cru SRST_PCIE4_POWER_UP>; 1253 reset-names = "pipe"; 1254 status = "disabled"; 1255 1256 pcie2x1l2_intc: legacy-interrupt-controller { 1257 interrupt-controller; 1258 #address-cells = <0>; 1259 #interrupt-cells = <1>; 1260 interrupt-parent = <&gic>; 1261 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 1262 }; 1263 }; 1264 1265 gmac1: ethernet@fe1c0000 { 1266 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 1267 reg = <0x0 0xfe1c0000 0x0 0x10000>; 1268 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "macirq", "eth_wake_irq"; 1271 rockchip,grf = <&sys_grf>; 1272 rockchip,php_grf = <&php_grf>; 1273 clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>, 1274 <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>; 1275 clock-names = "stmmaceth", "aclk_mac", 1276 "pclk_mac", "ptp_ref"; 1277 resets = <&cru SRST_A_GMAC1>; 1278 reset-names = "stmmaceth"; 1279 1280 snps,mixed-burst; 1281 snps,tso; 1282 1283 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1284 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1285 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1286 status = "disabled"; 1287 1288 mdio1: mdio { 1289 compatible = "snps,dwmac-mdio"; 1290 #address-cells = <0x1>; 1291 #size-cells = <0x0>; 1292 }; 1293 1294 gmac1_stmmac_axi_setup: stmmac-axi-config { 1295 snps,wr_osr_lmt = <4>; 1296 snps,rd_osr_lmt = <8>; 1297 snps,blen = <0 0 0 0 16 8 4>; 1298 }; 1299 1300 gmac1_mtl_rx_setup: rx-queues-config { 1301 snps,rx-queues-to-use = <2>; 1302 queue0 {}; 1303 queue1 {}; 1304 }; 1305 1306 gmac1_mtl_tx_setup: tx-queues-config { 1307 snps,tx-queues-to-use = <2>; 1308 queue0 {}; 1309 queue1 {}; 1310 }; 1311 }; 1312 1313 sata0: sata@fe210000 { 1314 compatible = "snps,dwc-ahci"; 1315 reg = <0 0xfe210000 0 0x1000>; 1316 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 1317 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; 1318 clock-names = "sata", "pmalive", "rxoob", "ref"; 1319 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 1320 interrupt-names = "hostc"; 1321 phys = <&combphy0_ps PHY_TYPE_SATA>; 1322 phy-names = "sata-phy"; 1323 ports-implemented = <0x1>; 1324 power-domains = <&power RK3588_PD_PHP>; 1325 status = "disabled"; 1326 }; 1327 1328 sata2: sata@fe230000 { 1329 compatible = "snps,dwc-ahci"; 1330 reg = <0 0xfe230000 0 0x1000>; 1331 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 1332 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; 1333 clock-names = "sata", "pmalive", "rxoob", "ref"; 1334 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 1335 interrupt-names = "hostc"; 1336 phys = <&combphy2_psu PHY_TYPE_SATA>; 1337 phy-names = "sata-phy"; 1338 ports-implemented = <0x1>; 1339 power-domains = <&power RK3588_PD_PHP>; 1340 status = "disabled"; 1341 }; 1342 1343 sfc: spi@fe2b0000 { 1344 compatible = "rockchip,sfc"; 1345 reg = <0x0 0xfe2b0000 0x0 0x4000>; 1346 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1348 clock-names = "clk_sfc", "hclk_sfc"; 1349 assigned-clocks = <&cru SCLK_SFC>; 1350 assigned-clock-rates = <100000000>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 sdmmc: mmc@fe2c0000 { 1357 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1358 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1359 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>, 1361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 1362 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; 1363 fifo-depth = <0x100>; 1364 max-frequency = <200000000>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 1367 status = "disabled"; 1368 }; 1369 1370 sdio: mmc@fe2d0000 { 1371 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 1372 reg = <0x0 0xfe2d0000 0x0 0x4000>; 1373 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 1375 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 1376 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1377 fifo-depth = <0x100>; 1378 max-frequency = <200000000>; 1379 status = "disabled"; 1380 }; 1381 1382 sdhci: mmc@fe2e0000 { 1383 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 1384 reg = <0x0 0xfe2e0000 0x0 0x10000>; 1385 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1386 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; 1387 assigned-clock-rates = <200000000>, <24000000>; 1388 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1389 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1390 <&cru TMCLK_EMMC>; 1391 clock-names = "core", "bus", "axi", "block", "timer"; 1392 max-frequency = <200000000>; 1393 status = "disabled"; 1394 }; 1395 1396 i2s0_8ch: i2s@fe470000 { 1397 compatible = "rockchip,rk3588-i2s-tdm"; 1398 reg = <0x0 0xfe470000 0x0 0x1000>; 1399 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1401 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1402 dmas = <&dmac0 0>, <&dmac0 1>; 1403 dma-names = "tx", "rx"; 1404 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1405 reset-names = "tx-m", "rx-m"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&i2s0_lrck 1408 &i2s0_sclk 1409 &i2s0_sdi0 1410 &i2s0_sdi1 1411 &i2s0_sdi2 1412 &i2s0_sdi3 1413 &i2s0_sdo0 1414 &i2s0_sdo1 1415 &i2s0_sdo2 1416 &i2s0_sdo3>; 1417 #sound-dai-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 i2s1_8ch: i2s@fe480000 { 1422 compatible = "rockchip,rk3588-i2s-tdm"; 1423 reg = <0x0 0xfe480000 0x0 0x1000>; 1424 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 1426 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1427 dmas = <&dmac0 2>, <&dmac0 3>; 1428 dma-names = "tx", "rx"; 1429 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1430 reset-names = "tx-m", "rx-m"; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&i2s1m0_lrck 1433 &i2s1m0_sclk 1434 &i2s1m0_sdi0 1435 &i2s1m0_sdi1 1436 &i2s1m0_sdi2 1437 &i2s1m0_sdi3 1438 &i2s1m0_sdo0 1439 &i2s1m0_sdo1 1440 &i2s1m0_sdo2 1441 &i2s1m0_sdo3>; 1442 #sound-dai-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 i2s2_2ch: i2s@fe490000 { 1447 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1448 reg = <0x0 0xfe490000 0x0 0x1000>; 1449 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1451 clock-names = "i2s_clk", "i2s_hclk"; 1452 dmas = <&dmac1 0>, <&dmac1 1>; 1453 dma-names = "tx", "rx"; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&i2s2m1_lrck 1456 &i2s2m1_sclk 1457 &i2s2m1_sdi 1458 &i2s2m1_sdo>; 1459 #sound-dai-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 i2s3_2ch: i2s@fe4a0000 { 1464 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 1465 reg = <0x0 0xfe4a0000 0x0 0x1000>; 1466 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 1468 clock-names = "i2s_clk", "i2s_hclk"; 1469 dmas = <&dmac1 2>, <&dmac1 3>; 1470 dma-names = "tx", "rx"; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&i2s3_lrck 1473 &i2s3_sclk 1474 &i2s3_sdi 1475 &i2s3_sdo>; 1476 #sound-dai-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 pdm0: pdm@fe4b0000 { 1481 compatible = "rockchip,rk3588-pdm"; 1482 reg = <0x0 0xfe4b0000 0x0 0x1000>; 1483 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 1484 clock-names = "pdm_clk", "pdm_hclk"; 1485 dmas = <&dmac0 4>; 1486 dma-names = "rx"; 1487 pinctrl-names = "default"; 1488 pinctrl-0 = <&pdm0m0_clk 1489 &pdm0m0_clk1 1490 &pdm0m0_sdi0 1491 &pdm0m0_sdi1 1492 &pdm0m0_sdi2 1493 &pdm0m0_sdi3>; 1494 #sound-dai-cells = <0>; 1495 status = "disabled"; 1496 }; 1497 1498 pdm1: pdm@fe4c0000 { 1499 compatible = "rockchip,rk3588-pdm"; 1500 reg = <0x0 0xfe4c0000 0x0 0x1000>; 1501 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 1502 clock-names = "pdm_clk", "pdm_hclk"; 1503 dmas = <&dmac1 4>; 1504 dma-names = "rx"; 1505 pinctrl-names = "default"; 1506 pinctrl-0 = <&pdm1m0_clk 1507 &pdm1m0_clk1 1508 &pdm1m0_sdi0 1509 &pdm1m0_sdi1 1510 &pdm1m0_sdi2 1511 &pdm1m0_sdi3>; 1512 #sound-dai-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 vad: vad@fe4d0000 { 1517 compatible = "rockchip,rk3588-vad"; 1518 reg = <0x0 0xfe4d0000 0x0 0x1000>; 1519 reg-names = "vad"; 1520 clocks = <&cru HCLK_VAD>; 1521 clock-names = "hclk"; 1522 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1523 rockchip,audio-src = <0>; 1524 rockchip,det-channel = <0>; 1525 rockchip,mode = <0>; 1526 #sound-dai-cells = <0>; 1527 status = "disabled"; 1528 }; 1529 1530 spdif_tx0: spdif-tx@fe4e0000 { 1531 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1532 reg = <0x0 0xfe4e0000 0x0 0x1000>; 1533 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1534 dmas = <&dmac0 5>; 1535 dma-names = "tx"; 1536 clock-names = "mclk", "hclk"; 1537 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&spdif0m0_tx>; 1540 #sound-dai-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 1544 spdif_tx1: spdif-tx@fe4f0000 { 1545 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 1546 reg = <0x0 0xfe4f0000 0x0 0x1000>; 1547 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1548 dmas = <&dmac1 5>; 1549 dma-names = "tx"; 1550 clock-names = "mclk", "hclk"; 1551 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&spdif1m0_tx>; 1554 #sound-dai-cells = <0>; 1555 status = "disabled"; 1556 }; 1557 1558 acdcdig_dsm: codec-digital@fe500000 { 1559 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 1560 reg = <0x0 0xfe500000 0x0 0x1000>; 1561 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 1562 clock-names = "dac", "pclk"; 1563 resets = <&cru SRST_DAC_ACDCDIG>; 1564 reset-names = "reset" ; 1565 rockchip,grf = <&sys_grf>; 1566 rockchip,pwm-output-mode; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&auddsm_pins>; 1569 #sound-dai-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 hwlock: hwspinlock@fe5a0000 { 1574 compatible = "rockchip,hwspinlock"; 1575 reg = <0 0xfe5a0000 0 0x100>; 1576 #hwlock-cells = <1>; 1577 }; 1578 1579 gic: interrupt-controller@fe600000 { 1580 compatible = "arm,gic-v3"; 1581 #interrupt-cells = <3>; 1582 #address-cells = <2>; 1583 #size-cells = <2>; 1584 ranges; 1585 interrupt-controller; 1586 1587 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 1588 <0x0 0xfe680000 0 0x100000>; /* GICR */ 1589 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1590 its: interrupt-controller@fe640000 { 1591 compatible = "arm,gic-v3-its"; 1592 msi-controller; 1593 #msi-cells = <1>; 1594 reg = <0x0 0xfe640000 0x0 0x20000>; 1595 }; 1596 }; 1597 1598 dmac0: dma-controller@fea10000 { 1599 compatible = "arm,pl330", "arm,primecell"; 1600 reg = <0x0 0xfea10000 0x0 0x4000>; 1601 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1603 clocks = <&cru ACLK_DMAC0>; 1604 clock-names = "apb_pclk"; 1605 #dma-cells = <1>; 1606 arm,pl330-periph-burst; 1607 }; 1608 1609 dmac1: dma-controller@fea30000 { 1610 compatible = "arm,pl330", "arm,primecell"; 1611 reg = <0x0 0xfea30000 0x0 0x4000>; 1612 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&cru ACLK_DMAC1>; 1615 clock-names = "apb_pclk"; 1616 #dma-cells = <1>; 1617 arm,pl330-periph-burst; 1618 }; 1619 1620 can0: can@fea50000 { 1621 compatible = "rockchip,canfd-1.0"; 1622 reg = <0x0 0xfea50000 0x0 0x1000>; 1623 iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1624 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 1625 clock-names = "baudclk", "apb_pclk"; 1626 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 1627 reset-names = "can", "can-apb"; 1628 pinctrl-names = "default"; 1629 pinctrl-0 = <&can0m0_pins>; 1630 tx-fifo-depth = <1>; 1631 rx-fifo-depth = <6>; 1632 status = "disabled"; 1633 }; 1634 1635 can1: can@fea60000 { 1636 compatible = "rockchip,canfd-1.0"; 1637 reg = <0x0 0xfea60000 0x0 0x1000>; 1638 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1639 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 1640 clock-names = "baudclk", "apb_pclk"; 1641 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 1642 reset-names = "can", "can-apb"; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&can1m0_pins>; 1645 tx-fifo-depth = <1>; 1646 rx-fifo-depth = <6>; 1647 status = "disabled"; 1648 }; 1649 1650 can2: can@fea70000 { 1651 compatible = "rockchip,canfd-1.0"; 1652 reg = <0x0 0xfea70000 0x0 0x1000>; 1653 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1654 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 1655 clock-names = "baudclk", "apb_pclk"; 1656 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 1657 reset-names = "can", "can-apb"; 1658 pinctrl-names = "default"; 1659 pinctrl-0 = <&can2m0_pins>; 1660 tx-fifo-depth = <1>; 1661 rx-fifo-depth = <6>; 1662 status = "disabled"; 1663 }; 1664 1665 hw_decompress: decompress@fea80000 { 1666 compatible = "rockchip,hw-decompress"; 1667 reg = <0x0 0xfea80000 0x0 0x1000>; 1668 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1669 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 1670 clock-names = "aclk", "dclk", "pclk"; 1671 resets = <&cru SRST_D_DECOM>; 1672 reset-names = "dresetn"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c1: i2c@fea90000 { 1677 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1678 reg = <0x0 0xfea90000 0x0 0x1000>; 1679 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1680 clock-names = "i2c", "pclk"; 1681 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&i2c1m0_xfer>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 status = "disabled"; 1687 }; 1688 1689 i2c2: i2c@feaa0000 { 1690 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1691 reg = <0x0 0xfeaa0000 0x0 0x1000>; 1692 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1693 clock-names = "i2c", "pclk"; 1694 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1695 pinctrl-names = "default"; 1696 pinctrl-0 = <&i2c2m0_xfer>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 status = "disabled"; 1700 }; 1701 1702 i2c3: i2c@feab0000 { 1703 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1704 reg = <0x0 0xfeab0000 0x0 0x1000>; 1705 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1706 clock-names = "i2c", "pclk"; 1707 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1708 pinctrl-names = "default"; 1709 pinctrl-0 = <&i2c3m0_xfer>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 i2c4: i2c@feac0000 { 1716 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1717 reg = <0x0 0xfeac0000 0x0 0x1000>; 1718 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1719 clock-names = "i2c", "pclk"; 1720 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&i2c4m0_xfer>; 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 status = "disabled"; 1726 }; 1727 1728 i2c5: i2c@fead0000 { 1729 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 1730 reg = <0x0 0xfead0000 0x0 0x1000>; 1731 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1732 clock-names = "i2c", "pclk"; 1733 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 1734 pinctrl-names = "default"; 1735 pinctrl-0 = <&i2c5m0_xfer>; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 status = "disabled"; 1739 }; 1740 1741 rktimer: timer@feae0000 { 1742 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 1743 reg = <0x0 0xfeae0000 0x0 0x20>; 1744 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1745 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 1746 clock-names = "pclk", "timer"; 1747 }; 1748 1749 wdt: watchdog@feaf0000 { 1750 compatible = "snps,dw-wdt"; 1751 reg = <0x0 0xfeaf0000 0x0 0x100>; 1752 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1753 clock-names = "tclk", "pclk"; 1754 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1755 status = "disabled"; 1756 }; 1757 1758 spi0: spi@feb00000 { 1759 compatible = "rockchip,rk3066-spi"; 1760 reg = <0x0 0xfeb00000 0x0 0x1000>; 1761 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1765 clock-names = "spiclk", "apb_pclk"; 1766 dmas = <&dmac0 14>, <&dmac0 15>; 1767 dma-names = "tx", "rx"; 1768 pinctrl-names = "default", "high_speed"; 1769 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1770 pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; 1771 num-cs = <2>; 1772 status = "disabled"; 1773 }; 1774 1775 spi1: spi@feb10000 { 1776 compatible = "rockchip,rk3066-spi"; 1777 reg = <0x0 0xfeb10000 0x0 0x1000>; 1778 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1782 clock-names = "spiclk", "apb_pclk"; 1783 dmas = <&dmac0 16>, <&dmac0 17>; 1784 dma-names = "tx", "rx"; 1785 pinctrl-names = "default", "high_speed"; 1786 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 1787 pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>; 1788 num-cs = <2>; 1789 status = "disabled"; 1790 }; 1791 1792 spi2: spi@feb20000 { 1793 compatible = "rockchip,rk3066-spi"; 1794 reg = <0x0 0xfeb20000 0x0 0x1000>; 1795 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1796 #address-cells = <1>; 1797 #size-cells = <0>; 1798 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1799 clock-names = "spiclk", "apb_pclk"; 1800 dmas = <&dmac1 15>, <&dmac1 16>; 1801 dma-names = "tx", "rx"; 1802 pinctrl-names = "default", "high_speed"; 1803 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1804 pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; 1805 num-cs = <2>; 1806 status = "disabled"; 1807 }; 1808 1809 spi3: spi@feb30000 { 1810 compatible = "rockchip,rk3066-spi"; 1811 reg = <0x0 0xfeb30000 0x0 0x1000>; 1812 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1816 clock-names = "spiclk", "apb_pclk"; 1817 dmas = <&dmac1 17>, <&dmac1 18>; 1818 dma-names = "tx", "rx"; 1819 pinctrl-names = "default", "high_speed"; 1820 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 1821 pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>; 1822 num-cs = <2>; 1823 status = "disabled"; 1824 }; 1825 1826 uart1: serial@feb40000 { 1827 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1828 reg = <0x0 0xfeb40000 0x0 0x100>; 1829 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1831 clock-names = "baudclk", "apb_pclk"; 1832 reg-shift = <2>; 1833 reg-io-width = <4>; 1834 dmas = <&dmac0 8>, <&dmac0 9>; 1835 pinctrl-names = "default"; 1836 pinctrl-0 = <&uart1m0_xfer>; 1837 status = "disabled"; 1838 }; 1839 1840 uart2: serial@feb50000 { 1841 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1842 reg = <0x0 0xfeb50000 0x0 0x100>; 1843 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 1844 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1845 clock-names = "baudclk", "apb_pclk"; 1846 reg-shift = <2>; 1847 reg-io-width = <4>; 1848 dmas = <&dmac0 10>, <&dmac0 11>; 1849 pinctrl-names = "default"; 1850 pinctrl-0 = <&uart2m0_xfer>; 1851 status = "disabled"; 1852 }; 1853 1854 uart3: serial@feb60000 { 1855 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1856 reg = <0x0 0xfeb60000 0x0 0x100>; 1857 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 1858 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1859 clock-names = "baudclk", "apb_pclk"; 1860 reg-shift = <2>; 1861 reg-io-width = <4>; 1862 dmas = <&dmac0 12>, <&dmac0 13>; 1863 pinctrl-names = "default"; 1864 pinctrl-0 = <&uart3m0_xfer>; 1865 status = "disabled"; 1866 }; 1867 1868 uart4: serial@feb70000 { 1869 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1870 reg = <0x0 0xfeb70000 0x0 0x100>; 1871 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1872 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1873 clock-names = "baudclk", "apb_pclk"; 1874 reg-shift = <2>; 1875 reg-io-width = <4>; 1876 dmas = <&dmac1 9>, <&dmac1 10>; 1877 pinctrl-names = "default"; 1878 pinctrl-0 = <&uart4m0_xfer>; 1879 status = "disabled"; 1880 }; 1881 1882 uart5: serial@feb80000 { 1883 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1884 reg = <0x0 0xfeb80000 0x0 0x100>; 1885 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 1886 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1887 clock-names = "baudclk", "apb_pclk"; 1888 reg-shift = <2>; 1889 reg-io-width = <4>; 1890 dmas = <&dmac1 11>, <&dmac1 12>; 1891 pinctrl-names = "default"; 1892 pinctrl-0 = <&uart5m0_xfer>; 1893 status = "disabled"; 1894 }; 1895 1896 uart6: serial@feb90000 { 1897 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1898 reg = <0x0 0xfeb90000 0x0 0x100>; 1899 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1900 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1901 clock-names = "baudclk", "apb_pclk"; 1902 reg-shift = <2>; 1903 reg-io-width = <4>; 1904 dmas = <&dmac1 13>, <&dmac1 14>; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&uart6m0_xfer>; 1907 status = "disabled"; 1908 }; 1909 1910 uart7: serial@feba0000 { 1911 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1912 reg = <0x0 0xfeba0000 0x0 0x100>; 1913 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1915 clock-names = "baudclk", "apb_pclk"; 1916 reg-shift = <2>; 1917 reg-io-width = <4>; 1918 dmas = <&dmac2 7>, <&dmac2 8>; 1919 pinctrl-names = "default"; 1920 pinctrl-0 = <&uart7m0_xfer>; 1921 status = "disabled"; 1922 }; 1923 1924 uart8: serial@febb0000 { 1925 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1926 reg = <0x0 0xfebb0000 0x0 0x100>; 1927 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1929 clock-names = "baudclk", "apb_pclk"; 1930 reg-shift = <2>; 1931 reg-io-width = <4>; 1932 dmas = <&dmac2 9>, <&dmac2 10>; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&uart8m0_xfer>; 1935 status = "disabled"; 1936 }; 1937 1938 uart9: serial@febc0000 { 1939 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 1940 reg = <0x0 0xfebc0000 0x0 0x100>; 1941 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1943 clock-names = "baudclk", "apb_pclk"; 1944 reg-shift = <2>; 1945 reg-io-width = <4>; 1946 dmas = <&dmac2 11>, <&dmac2 12>; 1947 pinctrl-names = "default"; 1948 pinctrl-0 = <&uart9m0_xfer>; 1949 status = "disabled"; 1950 }; 1951 1952 pwm4: pwm@febd0000 { 1953 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1954 reg = <0x0 0xfebd0000 0x0 0x10>; 1955 #pwm-cells = <3>; 1956 pinctrl-names = "active"; 1957 pinctrl-0 = <&pwm4m0_pins>; 1958 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1959 clock-names = "pwm", "pclk"; 1960 status = "disabled"; 1961 }; 1962 1963 pwm5: pwm@febd0010 { 1964 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1965 reg = <0x0 0xfebd0010 0x0 0x10>; 1966 #pwm-cells = <3>; 1967 pinctrl-names = "active"; 1968 pinctrl-0 = <&pwm5m0_pins>; 1969 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1970 clock-names = "pwm", "pclk"; 1971 status = "disabled"; 1972 }; 1973 1974 pwm6: pwm@febd0020 { 1975 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1976 reg = <0x0 0xfebd0020 0x0 0x10>; 1977 #pwm-cells = <3>; 1978 pinctrl-names = "active"; 1979 pinctrl-0 = <&pwm6m0_pins>; 1980 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1981 clock-names = "pwm", "pclk"; 1982 status = "disabled"; 1983 }; 1984 1985 pwm7: pwm@febd0030 { 1986 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 1987 reg = <0x0 0xfebd0030 0x0 0x10>; 1988 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1990 #pwm-cells = <3>; 1991 pinctrl-names = "active"; 1992 pinctrl-0 = <&pwm7m0_pins>; 1993 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1994 clock-names = "pwm", "pclk"; 1995 status = "disabled"; 1996 }; 1997 1998 pwm8: pwm@febe0000 { 1999 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2000 reg = <0x0 0xfebe0000 0x0 0x10>; 2001 #pwm-cells = <3>; 2002 pinctrl-names = "active"; 2003 pinctrl-0 = <&pwm8m0_pins>; 2004 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2005 clock-names = "pwm", "pclk"; 2006 status = "disabled"; 2007 }; 2008 2009 pwm9: pwm@febe0010 { 2010 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2011 reg = <0x0 0xfebe0010 0x0 0x10>; 2012 #pwm-cells = <3>; 2013 pinctrl-names = "active"; 2014 pinctrl-0 = <&pwm9m0_pins>; 2015 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2016 clock-names = "pwm", "pclk"; 2017 status = "disabled"; 2018 }; 2019 2020 pwm10: pwm@febe0020 { 2021 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2022 reg = <0x0 0xfebe0020 0x0 0x10>; 2023 #pwm-cells = <3>; 2024 pinctrl-names = "active"; 2025 pinctrl-0 = <&pwm10m0_pins>; 2026 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2027 clock-names = "pwm", "pclk"; 2028 status = "disabled"; 2029 }; 2030 2031 pwm11: pwm@febe0030 { 2032 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2033 reg = <0x0 0xfebe0030 0x0 0x10>; 2034 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2036 #pwm-cells = <3>; 2037 pinctrl-names = "active"; 2038 pinctrl-0 = <&pwm11m0_pins>; 2039 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 2040 clock-names = "pwm", "pclk"; 2041 status = "disabled"; 2042 }; 2043 2044 pwm12: pwm@febf0000 { 2045 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2046 reg = <0x0 0xfebf0000 0x0 0x10>; 2047 #pwm-cells = <3>; 2048 pinctrl-names = "active"; 2049 pinctrl-0 = <&pwm12m0_pins>; 2050 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2051 clock-names = "pwm", "pclk"; 2052 status = "disabled"; 2053 }; 2054 2055 pwm13: pwm@febf0010 { 2056 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2057 reg = <0x0 0xfebf0010 0x0 0x10>; 2058 #pwm-cells = <3>; 2059 pinctrl-names = "active"; 2060 pinctrl-0 = <&pwm13m0_pins>; 2061 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2062 clock-names = "pwm", "pclk"; 2063 status = "disabled"; 2064 }; 2065 2066 pwm14: pwm@febf0020 { 2067 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2068 reg = <0x0 0xfebf0020 0x0 0x10>; 2069 #pwm-cells = <3>; 2070 pinctrl-names = "active"; 2071 pinctrl-0 = <&pwm14m0_pins>; 2072 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2073 clock-names = "pwm", "pclk"; 2074 status = "disabled"; 2075 }; 2076 2077 pwm15: pwm@febf0030 { 2078 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2079 reg = <0x0 0xfebf0030 0x0 0x10>; 2080 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 2082 #pwm-cells = <3>; 2083 pinctrl-names = "active"; 2084 pinctrl-0 = <&pwm15m0_pins>; 2085 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 2086 clock-names = "pwm", "pclk"; 2087 status = "disabled"; 2088 }; 2089 2090 tsadc: tsadc@fec00000 { 2091 compatible = "rockchip,rk3588-tsadc"; 2092 reg = <0x0 0xfec00000 0x0 0x400>; 2093 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 2094 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 2095 clock-names = "tsadc", "apb_pclk"; 2096 assigned-clocks = <&cru CLK_TSADC>; 2097 assigned-clock-rates = <2000000>; 2098 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 2099 reset-names = "tsadc", "tsadc-apb"; 2100 #thermal-sensor-cells = <1>; 2101 rockchip,hw-tshut-temp = <120000>; 2102 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 2103 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 2104 pinctrl-names = "gpio", "otpout"; 2105 pinctrl-0 = <&tsadc_gpio_func>; 2106 pinctrl-1 = <&tsadc_shut_org>; 2107 status = "disabled"; 2108 }; 2109 2110 saradc: saradc@fec10000 { 2111 compatible = "rockchip,rk3588-saradc"; 2112 reg = <0x0 0xfec10000 0x0 0x10000>; 2113 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 2114 #io-channel-cells = <1>; 2115 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 2116 clock-names = "saradc", "apb_pclk"; 2117 resets = <&cru SRST_P_SARADC>; 2118 reset-names = "saradc-apb"; 2119 status = "disabled"; 2120 }; 2121 2122 mailbox0: mailbox@fec60000 { 2123 compatible = "rockchip,rk3588-mailbox", 2124 "rockchip,rk3368-mailbox"; 2125 reg = <0x0 0xfec60000 0x0 0x200>; 2126 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2130 clocks = <&cru PCLK_MAILBOX0>; 2131 clock-names = "pclk_mailbox"; 2132 #mbox-cells = <1>; 2133 status = "disabled"; 2134 }; 2135 2136 mailbox1: mailbox@fec70000 { 2137 compatible = "rockchip,rk3588-mailbox", 2138 "rockchip,rk3368-mailbox"; 2139 reg = <0x0 0xfec70000 0x0 0x200>; 2140 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2144 clocks = <&cru PCLK_MAILBOX1>; 2145 clock-names = "pclk_mailbox"; 2146 #mbox-cells = <1>; 2147 status = "disabled"; 2148 }; 2149 2150 i2c6: i2c@fec80000 { 2151 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2152 reg = <0x0 0xfec80000 0x0 0x1000>; 2153 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 2154 clock-names = "i2c", "pclk"; 2155 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 2156 pinctrl-names = "default"; 2157 pinctrl-0 = <&i2c6m0_xfer>; 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 status = "disabled"; 2161 }; 2162 2163 i2c7: i2c@fec90000 { 2164 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2165 reg = <0x0 0xfec90000 0x0 0x1000>; 2166 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 2167 clock-names = "i2c", "pclk"; 2168 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 2169 pinctrl-names = "default"; 2170 pinctrl-0 = <&i2c7m0_xfer>; 2171 #address-cells = <1>; 2172 #size-cells = <0>; 2173 status = "disabled"; 2174 }; 2175 2176 i2c8: i2c@feca0000 { 2177 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2178 reg = <0x0 0xfeca0000 0x0 0x1000>; 2179 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 2180 clock-names = "i2c", "pclk"; 2181 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 2182 pinctrl-names = "default"; 2183 pinctrl-0 = <&i2c8m0_xfer>; 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 status = "disabled"; 2187 }; 2188 2189 spi4: spi@fecb0000 { 2190 compatible = "rockchip,rk3066-spi"; 2191 reg = <0x0 0xfecb0000 0x0 0x1000>; 2192 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 2196 clock-names = "spiclk", "apb_pclk"; 2197 dmas = <&dmac2 13>, <&dmac2 14>; 2198 dma-names = "tx", "rx"; 2199 pinctrl-names = "default", "high_speed"; 2200 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 2201 pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>; 2202 num-cs = <2>; 2203 status = "disabled"; 2204 }; 2205 2206 otp: otp@fecc0000 { 2207 compatible = "rockchip,rk3588-otp"; 2208 reg = <0x0 0xfecc0000 0x0 0x400>; 2209 #address-cells = <1>; 2210 #size-cells = <1>; 2211 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 2212 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 2213 clock-names = "otpc", "apb", "arb", "phy"; 2214 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 2215 <&cru SRST_OTPC_ARB>; 2216 reset-names = "otpc", "apb", "arb"; 2217 }; 2218 2219 mailbox2: mailbox@fece0000 { 2220 compatible = "rockchip,rk3588-mailbox", 2221 "rockchip,rk3368-mailbox"; 2222 reg = <0x0 0xfece0000 0x0 0x200>; 2223 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&cru PCLK_MAILBOX2>; 2228 clock-names = "pclk_mailbox"; 2229 #mbox-cells = <1>; 2230 status = "disabled"; 2231 }; 2232 2233 dmac2: dma-controller@fed10000 { 2234 compatible = "arm,pl330", "arm,primecell"; 2235 reg = <0x0 0xfed10000 0x0 0x4000>; 2236 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2238 clocks = <&cru ACLK_DMAC2>; 2239 clock-names = "apb_pclk"; 2240 #dma-cells = <1>; 2241 arm,pl330-periph-burst; 2242 }; 2243 2244 hdptxphy0: phy@fed60000 { 2245 compatible = "rockchip,rk3588-hdptx-phy"; 2246 reg = <0x0 0xfed60000 0x0 0x2000>; 2247 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 2248 clock-names = "ref", "apb"; 2249 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 2250 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 2251 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 2252 <&cru SRST_HDPTX0_LCPLL>; 2253 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 2254 "lcpll"; 2255 rockchip,grf = <&hdptxphy0_grf>; 2256 #phy-cells = <0>; 2257 status = "disabled"; 2258 }; 2259 2260 usbdp_phy0: phy@fed80000 { 2261 compatible = "rockchip,rk3588-usbdp-phy"; 2262 reg = <0x0 0xfed80000 0x0 0x10000>; 2263 rockchip,usb-grf = <&usb_grf>; 2264 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 2265 rockchip,vo-grf = <&vo0_grf>; 2266 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 2267 <&cru CLK_USBDP_PHY0_IMMORTAL>, 2268 <&cru PCLK_USBDPPHY0>; 2269 clock-names = "refclk", "immortal", "pclk"; 2270 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 2271 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 2272 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 2273 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 2274 <&cru SRST_P_USBDPPHY0>; 2275 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 2276 status = "disabled"; 2277 2278 usbdp_phy0_dp: dp-port { 2279 #phy-cells = <0>; 2280 status = "disabled"; 2281 }; 2282 2283 usbdp_phy0_u3: u3-port { 2284 #phy-cells = <0>; 2285 status = "disabled"; 2286 }; 2287 }; 2288 2289 combphy0_ps: phy@fee00000 { 2290 compatible = "rockchip,rk3588-naneng-combphy"; 2291 reg = <0x0 0xfee00000 0x0 0x100>; 2292 #phy-cells = <1>; 2293 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; 2294 clock-names = "refclk", "apbclk"; 2295 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 2296 assigned-clock-rates = <100000000>; 2297 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 2298 reset-names = "combphy-apb", "combphy"; 2299 rockchip,pipe-grf = <&php_grf>; 2300 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 2301 status = "disabled"; 2302 }; 2303 2304 combphy2_psu: phy@fee20000 { 2305 compatible = "rockchip,rk3588-naneng-combphy"; 2306 reg = <0x0 0xfee20000 0x0 0x100>; 2307 #phy-cells = <1>; 2308 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; 2309 clock-names = "refclk", "apbclk"; 2310 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 2311 assigned-clock-rates = <100000000>; 2312 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 2313 reset-names = "combphy-apb", "combphy"; 2314 rockchip,pipe-grf = <&php_grf>; 2315 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 2316 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 2317 status = "disabled"; 2318 }; 2319 2320 pinctrl: pinctrl { 2321 compatible = "rockchip,rk3588-pinctrl"; 2322 rockchip,grf = <&ioc>; 2323 #address-cells = <2>; 2324 #size-cells = <2>; 2325 ranges; 2326 2327 gpio0: gpio@fd8a0000 { 2328 compatible = "rockchip,gpio-bank"; 2329 reg = <0x0 0xfd8a0000 0x0 0x100>; 2330 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2332 2333 gpio-controller; 2334 #gpio-cells = <2>; 2335 gpio-ranges = <&pinctrl 0 0 32>; 2336 interrupt-controller; 2337 #interrupt-cells = <2>; 2338 }; 2339 2340 gpio1: gpio@fec20000 { 2341 compatible = "rockchip,gpio-bank"; 2342 reg = <0x0 0xfec20000 0x0 0x100>; 2343 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 2344 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2345 2346 gpio-controller; 2347 #gpio-cells = <2>; 2348 gpio-ranges = <&pinctrl 0 32 32>; 2349 interrupt-controller; 2350 #interrupt-cells = <2>; 2351 }; 2352 2353 gpio2: gpio@fec30000 { 2354 compatible = "rockchip,gpio-bank"; 2355 reg = <0x0 0xfec30000 0x0 0x100>; 2356 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 2357 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2358 2359 gpio-controller; 2360 #gpio-cells = <2>; 2361 gpio-ranges = <&pinctrl 0 64 32>; 2362 interrupt-controller; 2363 #interrupt-cells = <2>; 2364 }; 2365 2366 gpio3: gpio@fec40000 { 2367 compatible = "rockchip,gpio-bank"; 2368 reg = <0x0 0xfec40000 0x0 0x100>; 2369 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 2370 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2371 2372 gpio-controller; 2373 #gpio-cells = <2>; 2374 gpio-ranges = <&pinctrl 0 96 32>; 2375 interrupt-controller; 2376 #interrupt-cells = <2>; 2377 }; 2378 2379 gpio4: gpio@fec50000 { 2380 compatible = "rockchip,gpio-bank"; 2381 reg = <0x0 0xfec50000 0x0 0x100>; 2382 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 2383 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2384 2385 gpio-controller; 2386 #gpio-cells = <2>; 2387 gpio-ranges = <&pinctrl 0 128 32>; 2388 interrupt-controller; 2389 #interrupt-cells = <2>; 2390 }; 2391 }; 2392}; 2393 2394#include "rk3588s-pinctrl.dtsi" 2395