1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/phy/phy-snps-pcie3.h> 7#include "rk3588s.dtsi" 8#include "rk3588-vccio3-pinctrl.dtsi" 9 10/ { 11 aliases { 12 edp0 = &edp0; 13 edp1 = &edp1; 14 ethernet0 = &gmac0; 15 hdptx0 = &hdptxphy0; 16 hdptx1 = &hdptxphy1; 17 }; 18 19 usbdrd3_1: usbdrd3_1 { 20 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 21 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 22 <&cru ACLK_USB3OTG1>; 23 clock-names = "ref", "suspend", "bus"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 status = "disabled"; 28 29 usbdrd_dwc3_1: usb@fc400000 { 30 compatible = "snps,dwc3"; 31 reg = <0x0 0xfc400000 0x0 0x400000>; 32 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 33 power-domains = <&power RK3588_PD_USB>; 34 resets = <&cru SRST_A_USB3OTG1>; 35 reset-names = "usb3-otg"; 36 dr_mode = "host"; 37 phys = <&u2phy1_otg>; 38 phy-names = "usb2-phy"; 39 phy_type = "utmi_wide"; 40 snps,dis_enblslpm_quirk; 41 snps,dis-u2-freeclk-exists-quirk; 42 snps,dis-del-phy-power-chg-quirk; 43 snps,dis-tx-ipgap-linecheck-quirk; 44 status = "disabled"; 45 }; 46 }; 47 48 pcie30_phy_grf: syscon@fd5b8000 { 49 compatible = "rockchip,pcie30-phy-grf", "syscon"; 50 reg = <0x0 0xfd5b8000 0x0 0x10000>; 51 }; 52 53 pipe_phy1_grf: syscon@fd5c0000 { 54 compatible = "rockchip,pipe-phy-grf", "syscon"; 55 reg = <0x0 0xfd5c0000 0x0 0x100>; 56 }; 57 58 usbdpphy1_grf: syscon@fd5cc000 { 59 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 60 reg = <0x0 0xfd5cc000 0x0 0x4000>; 61 }; 62 63 usb2phy1_grf: syscon@fd5d4000 { 64 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 65 "simple-mfd"; 66 reg = <0x0 0xfd5d4000 0x0 0x4000>; 67 #address-cells = <1>; 68 #size-cells = <1>; 69 70 u2phy1: usb2-phy@4000 { 71 compatible = "rockchip,rk3588-usb2phy"; 72 reg = <0x4000 0x10>; 73 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 74 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 75 reset-names = "phy", "apb"; 76 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 77 clock-names = "phyclk"; 78 #clock-cells = <0>; 79 status = "disabled"; 80 81 u2phy1_otg: otg-port { 82 #phy-cells = <0>; 83 status = "disabled"; 84 }; 85 }; 86 }; 87 88 hdptxphy1_grf: syscon@fd5e4000 { 89 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 90 reg = <0x0 0xfd5e4000 0x0 0x100>; 91 }; 92 93 spdif_tx5: spdif-tx@fddb8000 { 94 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 95 reg = <0x0 0xfddb8000 0x0 0x1000>; 96 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 97 dmas = <&dmac1 22>; 98 dma-names = "tx"; 99 clock-names = "mclk", "hclk"; 100 clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>; 101 #sound-dai-cells = <0>; 102 status = "disabled"; 103 }; 104 105 i2s8_8ch: i2s@fddc8000 { 106 compatible = "rockchip,rk3588-i2s-tdm"; 107 reg = <0x0 0xfddc8000 0x0 0x1000>; 108 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 110 clock-names = "mclk_tx", "hclk"; 111 dmas = <&dmac2 22>; 112 dma-names = "tx"; 113 resets = <&cru SRST_M_I2S8_8CH_TX>; 114 reset-names = "tx-m"; 115 #sound-dai-cells = <0>; 116 status = "disabled"; 117 }; 118 119 spdif_tx4: spdif-tx@fdde8000 { 120 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 121 reg = <0x0 0xfdde8000 0x0 0x1000>; 122 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 123 dmas = <&dmac1 8>; 124 dma-names = "tx"; 125 clock-names = "mclk", "hclk"; 126 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 127 #sound-dai-cells = <0>; 128 status = "disabled"; 129 }; 130 131 i2s6_8ch: i2s@fddf4000 { 132 compatible = "rockchip,rk3588-i2s-tdm"; 133 reg = <0x0 0xfddf4000 0x0 0x1000>; 134 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 136 clock-names = "mclk_tx", "hclk"; 137 dmas = <&dmac2 4>; 138 dma-names = "tx"; 139 resets = <&cru SRST_M_I2S6_8CH_TX>; 140 reset-names = "tx-m"; 141 #sound-dai-cells = <0>; 142 status = "disabled"; 143 }; 144 145 i2s7_8ch: i2s@fddf8000 { 146 compatible = "rockchip,rk3588-i2s-tdm"; 147 reg = <0x0 0xfddf8000 0x0 0x1000>; 148 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 150 clock-names = "mclk_rx", "hclk"; 151 dmas = <&dmac2 21>; 152 dma-names = "rx"; 153 resets = <&cru SRST_M_I2S7_8CH_RX>; 154 reset-names = "rx-m"; 155 #sound-dai-cells = <0>; 156 status = "disabled"; 157 }; 158 159 i2s10_8ch: i2s@fde00000 { 160 compatible = "rockchip,rk3588-i2s-tdm"; 161 reg = <0x0 0xfde00000 0x0 0x1000>; 162 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 164 clock-names = "mclk_rx", "hclk"; 165 dmas = <&dmac2 24>; 166 dma-names = "rx"; 167 resets = <&cru SRST_M_I2S10_8CH_RX>; 168 reset-names = "rx-m"; 169 #sound-dai-cells = <0>; 170 status = "disabled"; 171 }; 172 173 spdif_rx1: spdif-rx@fde10000 { 174 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 175 reg = <0x0 0xfde10000 0x0 0x1000>; 176 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; 178 clock-names = "mclk", "hclk"; 179 dmas = <&dmac0 22>; 180 dma-names = "rx"; 181 resets = <&cru SRST_M_SPDIFRX1>; 182 reset-names = "spdifrx-m"; 183 #sound-dai-cells = <0>; 184 status = "disabled"; 185 }; 186 187 spdif_rx2: spdif-rx@fde18000 { 188 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 189 reg = <0x0 0xfde18000 0x0 0x1000>; 190 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; 192 clock-names = "mclk", "hclk"; 193 dmas = <&dmac0 23>; 194 dma-names = "rx"; 195 resets = <&cru SRST_M_SPDIFRX2>; 196 reset-names = "spdifrx-m"; 197 #sound-dai-cells = <0>; 198 status = "disabled"; 199 }; 200 201 edp1: edp@fded0000 { 202 compatible = "rockchip,rk3588-edp"; 203 reg = <0x0 0xfded0000 0x0 0x1000>; 204 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, 206 <&cru CLK_EDP1_200M>; 207 clock-names = "dp", "pclk", "spdif"; 208 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; 209 reset-names = "dp", "apb"; 210 phys = <&hdptxphy1>; 211 phy-names = "dp"; 212 power-domains = <&power RK3588_PD_VO1>; 213 rockchip,grf = <&vo1_grf>; 214 status = "disabled"; 215 }; 216 217 pcie3x4: pcie@fe150000 { 218 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 219 #address-cells = <3>; 220 #size-cells = <2>; 221 bus-range = <0x00 0x0f>; 222 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 223 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 224 <&cru CLK_PCIE_AUX0>; 225 clock-names = "aclk_mst", "aclk_slv", 226 "aclk_dbi", "pclk", "aux"; 227 device_type = "pci"; 228 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 233 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 234 #interrupt-cells = <1>; 235 interrupt-map-mask = <0 0 0 7>; 236 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 237 <0 0 0 2 &pcie3x4_intc 1>, 238 <0 0 0 3 &pcie3x4_intc 2>, 239 <0 0 0 4 &pcie3x4_intc 3>; 240 linux,pci-domain = <0>; 241 num-ib-windows = <16>; 242 num-ob-windows = <16>; 243 max-link-speed = <3>; 244 msi-map = <0x0000 &its 0x0000 0x1000>; 245 num-lanes = <4>; 246 phys = <&pcie30phy>; 247 phy-names = "pcie-phy"; 248 power-domains = <&power RK3588_PD_PCIE>; 249 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 250 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 251 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000 252 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; 253 reg = <0xa 0x40000000 0x0 0x400000>, 254 <0x0 0xfe150000 0x0 0x10000>; 255 reg-names = "pcie-dbi", "pcie-apb"; 256 resets = <&cru SRST_PCIE0_POWER_UP>; 257 reset-names = "pipe"; 258 status = "disabled"; 259 260 pcie3x4_intc: legacy-interrupt-controller { 261 interrupt-controller; 262 #address-cells = <0>; 263 #interrupt-cells = <1>; 264 interrupt-parent = <&gic>; 265 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>; 266 }; 267 }; 268 269 pcie3x2: pcie@fe160000 { 270 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 271 #address-cells = <3>; 272 #size-cells = <2>; 273 bus-range = <0x10 0x1f>; 274 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 275 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 276 <&cru CLK_PCIE_AUX1>; 277 clock-names = "aclk_mst", "aclk_slv", 278 "aclk_dbi", "pclk", "aux"; 279 device_type = "pci"; 280 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 285 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 286 #interrupt-cells = <1>; 287 interrupt-map-mask = <0 0 0 7>; 288 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 289 <0 0 0 2 &pcie3x2_intc 1>, 290 <0 0 0 3 &pcie3x2_intc 2>, 291 <0 0 0 4 &pcie3x2_intc 3>; 292 linux,pci-domain = <1>; 293 num-ib-windows = <16>; 294 num-ob-windows = <16>; 295 max-link-speed = <3>; 296 msi-map = <0x1000 &its 0x1000 0x1000>; 297 num-lanes = <2>; 298 phys = <&pcie30phy>; 299 phy-names = "pcie-phy"; 300 power-domains = <&power RK3588_PD_PHP>; 301 ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000 302 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000 303 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000 304 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; 305 reg = <0xa 0x40400000 0x0 0x400000>, 306 <0x0 0xfe160000 0x0 0x10000>; 307 reg-names = "pcie-dbi", "pcie-apb"; 308 resets = <&cru SRST_PCIE1_POWER_UP>; 309 reset-names = "pipe"; 310 status = "disabled"; 311 312 pcie3x2_intc: legacy-interrupt-controller { 313 interrupt-controller; 314 #address-cells = <0>; 315 #interrupt-cells = <1>; 316 interrupt-parent = <&gic>; 317 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; 318 }; 319 }; 320 321 pcie2x1l0: pcie@fe170000 { 322 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 323 #address-cells = <3>; 324 #size-cells = <2>; 325 bus-range = <0x20 0x2f>; 326 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 327 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 328 <&cru CLK_PCIE_AUX2>; 329 clock-names = "aclk_mst", "aclk_slv", 330 "aclk_dbi", "pclk", "aux"; 331 device_type = "pci"; 332 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 337 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 338 #interrupt-cells = <1>; 339 interrupt-map-mask = <0 0 0 7>; 340 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 341 <0 0 0 2 &pcie2x1l0_intc 1>, 342 <0 0 0 3 &pcie2x1l0_intc 2>, 343 <0 0 0 4 &pcie2x1l0_intc 3>; 344 linux,pci-domain = <2>; 345 num-ib-windows = <8>; 346 num-ob-windows = <8>; 347 max-link-speed = <2>; 348 msi-map = <0x2000 &its 0x2000 0x1000>; 349 num-lanes = <1>; 350 phys = <&combphy1_ps PHY_TYPE_PCIE>; 351 phy-names = "pcie-phy"; 352 power-domains = <&power RK3588_PD_PHP>; 353 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 354 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 355 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000 356 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; 357 reg = <0xa 0x40800000 0x0 0x400000>, 358 <0x0 0xfe170000 0x0 0x10000>; 359 reg-names = "pcie-dbi", "pcie-apb"; 360 resets = <&cru SRST_PCIE2_POWER_UP>; 361 reset-names = "pipe"; 362 status = "disabled"; 363 364 pcie2x1l0_intc: legacy-interrupt-controller { 365 interrupt-controller; 366 #address-cells = <0>; 367 #interrupt-cells = <1>; 368 interrupt-parent = <&gic>; 369 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>; 370 }; 371 }; 372 373 gmac0: ethernet@fe1b0000 { 374 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 375 reg = <0x0 0xfe1b0000 0x0 0x10000>; 376 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "macirq", "eth_wake_irq"; 379 rockchip,grf = <&sys_grf>; 380 rockchip,php_grf = <&php_grf>; 381 clocks = <&cru CLK_GMAC0>, <&cru ACLK_GMAC0>, 382 <&cru PCLK_GMAC0>, <&cru CLK_GMAC0_PTP_REF>; 383 clock-names = "stmmaceth", "aclk_mac", 384 "pclk_mac", "ptp_ref"; 385 resets = <&cru SRST_A_GMAC0>; 386 reset-names = "stmmaceth"; 387 388 snps,mixed-burst; 389 snps,tso; 390 391 snps,axi-config = <&gmac0_stmmac_axi_setup>; 392 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 393 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 394 status = "disabled"; 395 396 mdio0: mdio { 397 compatible = "snps,dwmac-mdio"; 398 #address-cells = <0x1>; 399 #size-cells = <0x0>; 400 }; 401 402 gmac0_stmmac_axi_setup: stmmac-axi-config { 403 snps,wr_osr_lmt = <4>; 404 snps,rd_osr_lmt = <8>; 405 snps,blen = <0 0 0 0 16 8 4>; 406 }; 407 408 gmac0_mtl_rx_setup: rx-queues-config { 409 snps,rx-queues-to-use = <2>; 410 queue0 {}; 411 queue1 {}; 412 }; 413 414 gmac0_mtl_tx_setup: tx-queues-config { 415 snps,tx-queues-to-use = <2>; 416 queue0 {}; 417 queue1 {}; 418 }; 419 }; 420 421 sata1: sata@fe220000 { 422 compatible = "snps,dwc-ahci"; 423 reg = <0 0xfe220000 0 0x1000>; 424 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 425 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>; 426 clock-names = "sata", "pmalive", "rxoob", "ref"; 427 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 428 interrupt-names = "hostc"; 429 phys = <&combphy1_ps PHY_TYPE_SATA>; 430 phy-names = "sata-phy"; 431 ports-implemented = <0x1>; 432 power-domains = <&power RK3588_PD_PHP>; 433 status = "disabled"; 434 }; 435 436 crypto: crypto@fe370000 { 437 compatible = "rockchip,rk3588-crypto"; 438 reg = <0x0 0xfe370000 0x0 0x4000>; 439 clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; 440 clock-names = "sclk_crypto", "apkclk_crypto"; 441 clock-frequency = <350000000>, <350000000>; 442 status = "disabled"; 443 }; 444 445 rng: rng@fe378000 { 446 compatible = "rockchip,trngv1"; 447 reg = <0x0 0xfe378000 0x0 0x200>; 448 status = "disabled"; 449 }; 450 451 hdptxphy1: phy@fed70000 { 452 compatible = "rockchip,rk3588-hdptx-phy"; 453 reg = <0x0 0xfed70000 0x0 0x2000>; 454 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 455 clock-names = "ref", "apb"; 456 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 457 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 458 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 459 <&cru SRST_HDPTX1_LCPLL>; 460 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 461 "lcpll"; 462 rockchip,grf = <&hdptxphy1_grf>; 463 #phy-cells = <0>; 464 status = "disabled"; 465 }; 466 467 usbdp_phy1: phy@fed90000 { 468 compatible = "rockchip,rk3588-usbdp-phy"; 469 reg = <0x0 0xfed90000 0x0 0x10000>; 470 rockchip,usb-grf = <&usb_grf>; 471 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 472 rockchip,vo-grf = <&vo0_grf>; 473 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 474 <&cru CLK_USBDP_PHY1_IMMORTAL>, 475 <&cru PCLK_USBDPPHY1>; 476 clock-names = "refclk", "immortal", "pclk"; 477 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 478 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 479 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 480 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 481 <&cru SRST_P_USBDPPHY1>; 482 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 483 status = "disabled"; 484 485 usbdp_phy1_dp: dp-port { 486 #phy-cells = <0>; 487 status = "disabled"; 488 }; 489 490 usbdp_phy1_u3: u3-port { 491 #phy-cells = <0>; 492 status = "disabled"; 493 }; 494 }; 495 496 combphy1_ps: phy@fee10000 { 497 compatible = "rockchip,rk3588-naneng-combphy"; 498 reg = <0x0 0xfee10000 0x0 0x100>; 499 #phy-cells = <1>; 500 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>; 501 clock-names = "refclk", "apbclk"; 502 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 503 assigned-clock-rates = <100000000>; 504 resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; 505 reset-names = "combphy-apb", "combphy"; 506 rockchip,pipe-grf = <&php_grf>; 507 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 508 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; 509 status = "disabled"; 510 }; 511 512 pcie30phy: phy@fee80000 { 513 compatible = "rockchip,rk3588-pcie3-phy"; 514 reg = <0x0 0xfee80000 0x0 0x20000>; 515 #phy-cells = <0>; 516 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 517 clock-names = "pclk"; 518 resets = <&cru SRST_PCIE30_PHY>; 519 reset-names = "phy"; 520 rockchip,pipe-grf = <&php_grf>; 521 rockchip,phy-grf = <&pcie30_phy_grf>; 522 status = "disabled"; 523 }; 524 525}; 526